I have not had time to keep up with rumors lately so perhaps this has already been discussed. I am not searching back through ~300 pages of speculation.
I see Turin information saying 128 Zen 5 cores or 192 Zen 5c cores. 192 Zen 5c cores make sense (16 cores * 12 CCDs). How do we get 128...
Seems like it should be named something else if it uses bumps.
Stix Halo looks more like just using desktop chiplets in mobile, except with big gpu + infinity cache in IO die. It doesn't seem like it brings much in the way of system design changes except for the on package memory. I was...
I don't have time to wade through this thread; seems to be a lot of off topic stuff recently.
Anyway, I was thinking about the CPUs used on MI300. They seem to be specialized to stack on top of the base die, but I don't know if they use SoIC or some micro-bump tech? The cpu doesn't really...
It would be great if they could do that, but it seems like the package may be too expensive. The Mi300 base die also likely doesn't contain anything other than HBM interfaces, GMI, and whatever they are using for the base die to base die links. I don't know if that is known yet? It doesn't...
It is a bit odd, there is still a big price difference between 6 or 8 cores and anything above that. A 6 core part with 32MB L3 is going to perform well for most games. Looking at the steam survey, 4 core parts are actually increasing. It was near 50% 6 core parts and now that is down near...
Intel tried to stay at 4 cores for the mainstream market for way too long so that they could charge really high prices for anything above that. AMD came along and offered a much more reasonalble price up to 16 cores and then dominated almost everything else with Epyc scalability. Above 4 was...
I don't think we will see a mixed chiplet with both types of cores in the same die, as some have talked about, but they appear to be going to mix dense and regular cores in APUs, if the rumors can be trusted. I was wondering if the dense and regular chiplets are actually made on the same...
I thought there was some patent about transparently switching a thread between a high and low performance core based on what the thread actually needs. This can be done in a transparent manner where the high performance and the low power core look like the same core to the OS. This would...
Edited a bit for clarity and readability.
No, I am not confusing anything. The post somewhere above seemed to imply 16 cpu chiplet parts, which would mean they would need 4 ports per quadrant, 16 total. I was refering to 6 to 8 cores per CCD for the 4 CCD devices. They are at rather low...
The genoa 4 CCD devices don't make too much sense, or at least, it doesn't seem to make that much sense for them to have dual GMI links. They are relatively low clocked parts, but they do have 6 to 8 cores, so it is unclear whether they can actually consume that much bandwidth. If they took an...
If it will have 16 CCDs, then that seems to imply that the IO die has an extra cpu link that is not currently being used? I wonder if they could build an 8 chiplet device with dual links per chiplet.
AMD already has a bunch of advantages here with a much higher bandwidth, more HBM, and a truly unified memory system compared to Grace-Hopper. Grace-Hopper will have higher capacity within the package, but only at around 500 GB/s to the LPDDR. AMD can build machines with SH5 gpus paired with...
They can get very dense SRAM cache on a process optimized for it. Since the infinity cache is connected to the compute die in MI300 with SoIC, it can be as fast as on-die caches. I don’t know if there is need in the hierarchy for an explicit memory side cache.
I initially thought that MI300...
The memory attached to the grace cpu appears to be unified with the HBM memory. It may not be exactly the same as AMD's implementation with HBM possibly set up more like cache, but it seems to be cache coherent between the LPDDR5x and the HBM. It isn't as tightly coupled as AMD has with their...
It looks like these are likely to be used in 8 socket systems, so that will be 1 TB or 1.5 TB for the 192 GB gpu only version. This may still be problematic for some HPC applications where they need to hold a large amount of data in memory. Multiple TB of system memory is sometimes required...
If you aren’t a victim of nvidia vendor lock-in practices, then there is reason to be interested. Also, you obviously have to be interested in such hardware in the first place. This is isn’t a gaming gpu.
I am more interested in the packaging tech and how it could be applied elsewhere. I...
Doesn't seem like much info on the package construction. They basically just confirmed the MI300A and MI300X products and that is about it. I skipped around a bit, but I don't think there was any mention of a cpu only version, but they have to connect a gpu only version to a cpu somehow...
AMD may be at a disadvantage if they do not have anything other than HBM on package and can't connect off package memory other than CXL. Grace-hopper has up to 512 GB LPDDR5x per module and up to 96 GB HBM3. AMD may only have 128 GB HBM3. Even in a 4s system, this would only be 512 GB vs. 2...
I remember an interview with an AMD person discussing this briefly quite a while ago, but I don't remember who it was or when. Such long bridges sounded problematic. It might be that they still run a SerDes type link, but run it through the embedded silicon to reduce power and increase speed...
We have seen some changes to the caches with different Zen generations, but I think Zen 5 is going to be changes to the whole cache hierarchy. This may be significantly more radical changes compared to zen 2 to Zen 3. I don't know whether that will result in big improvements though. Pushing...
I had initially thought that we would get almost everything stacked in the Zen 5 generation, but that just doesn't seem to be the case. The stacked silicon packages are more expensive and they add in some limitations. They generally require that chips be directly adjacent. The infinity fabric...
SP3 and SH5 cover different markets. The even the SP5 socket is problematic in some cases due to needing the board space for 12 DIMM slots per socket. There seems to be some board/chasis power limitations, at least for 2U systems. Some are not supporting the higher power consumption Genoa...
It has beeen speculated for a while. An SH5 article from Sept. 2021 on wccftech mentions the possibility of a Zen 4 cpu in SH5. The bandwidth would be ridiculous; I am not sure a Zen 4 chiplet can really make full use of it, so it might be overkill. Zen 5, if it has significant FP...
This doesn’t have anything about AI chiplets. Will the AI chiplets take the place of GPU chiplets? If it can operate as all GPU, then I guess they probably can mix and match any that they want. Perhaps the APU launches first with the other variants a little later.
I assume that the SH5 socket will have a larger max power than the SP5 socket, so it will be really interesting to see 96 cores with possibly a much larger power budget, if these actually exist. SH5 isn’t really the “data center” socket; that is SP5. SH5 is the HPC socket.
The base die are rectangular, so they only have 2 orientations. With the single LSI bridge, it seems like they would need to put the interface for it on both the top and the bottom of one edge of the base die with 1 interface going unused. It would be rotated 180 degrees for those on the left...
I assume the large green card is the sligshot network card. It appears to be raised up off the surface of the board. The white pieces around the cpus look raised up also, so perhaps some kind of ram coolers or baffles with DIMMS underneath? It is a very compact system probably without much...
I still don't know what you are trying to get at here. The virtual memory page size is often 4KB, but can be, and probably should be larger. I have noticed that most applications perform better with the 2 MB pages, probably due to less stress on the TLB. 4KB is very small when you have 1 TB...
IOPS in regard to L2/L3 caches?
There have been a lot of rumors saying that Zen 5 will have large, shared L2, but they could always be completely wrong. We have had large L2 cache chips in the past and many applications do very well with large L2. The old Core 2 Duo processors with 6 MB L2...
I saw some geekbench scores for M2 and some for possible Genoa. The single core still seems to be much higher for Apple M2.
This is the M2 cache structure (according to wikipedia):
L1 cache Performance cores 192+128 KB per core
Efficiency cores 128+64 KB per core
L2 cache...
The image of the LGA under an MI300 here looks almost exactly like genoa, except genoa appears to have two small circles at the corners in the area in the middle that Mi300 does not have...
I think there was some discussion of deliberatly adding extra TSVs for greater thermal conductivity, since copper has higher thermal conductivity than silicon. This may affect make thermal expansion issues worse though.
It isn't uncommon for HPC machines to have 512 GB to 1 TB of system memory per GPU. The latency of CXL is possibly not an issue with all of the SRAM and HBM in the system, but I would expect it to have memory expansion somewhere / somehow.
It seems very unlikely that AMD would spend time...
Maybe. I remember an interview with an AMD engineer where it sounded like they took something that was more intended for mobile and turned it into a super high bandwidth connection, so perhaps a standard TSMC tech, but not the original intended use.
I would not assume that Zen 5 will have a similar cache hierarchy to Zen 4. I expect it to be radically different. A lot depends on the yield of SoIC stacking. If yield is very high, then stacking on (or under) expensive compute die makes sense. For very expensive products, like MI300, it...
It may not be L3, although if L2 is much larger and shared, then L3 can move farther out. My initial thoughts for Zen 5 was larger L2 shared between multiple cores; I had been thinking 2 to 4 cores, but rumors have been saying all 8. Then possibly much smaller or stacked only L3. If cache is...
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The top diagram kind of looks like one of the MI300 slides, except possibly with two, rather than 4, cpu chiplets stacked on each end with possibly an FPGA / AI accelerator in the middle.
You would still have, possibly large, L2 and L1 caches on the compute die, so that could give them some area for stacking L3 cache on top without covering cores. It seems like it makes more sense to stack cache on top of IO though, which is part of why I was thinking of stacked cache on top of...
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