No Editing ?! :O
But yeah, IMO not using bold fonts for unread threads also makes it much harder to pick out interesting information.
No Editing ?! :OI also find the lack of editing in the new forums highly limiting.
Yes, that's my point. Every further expansion above it degrades latency, so latency uniformity with low latency is already gone at that point. The different approaches just decide by how much. CCX is totally uniform for 4 cores, complexity makes more cores unlikely. Ring bus isn't but I guess one could argue that up to some amount of cores the increase is negligible. 85ns worst case is 2.5 times the best case of 34ns. Mesh has high uniformity with high power consumption; while worst case is just 19% above the best, the best case starts at 69.3ns, close to the ring bus' worst.But AMDs current CCX implementation is really only uniform for 4 cores with a reasonable amount of direct links between them
IPC = Instructions Per Clock.
It's something that many seem to now equate to Instructions Per Core - when it never meant this.
So you'd be looking at an "Instructions Per Core" improvement of 1.13 x 1.13 ~ 1.28 [considering both IPC and clock rate]
Yes, that's my point. Every further expansion above it degrades latency, so latency uniformity with low latency is already gone at that point. The different approaches just decide by how much. CCX is totally uniform for 4 cores, complexity makes more cores unlikely. Ring bus isn't but I guess one could argue that up to some amount of cores the increase is negligible. 85ns worst case is 2.5 times the best case of 34ns. Mesh has high uniformity with high power consumption; while worst case is just 19% above the best, the best case starts at 69.3ns, close to the ring bus' worst.
AMD obviously decided that there must be other feasible approaches. Let's see how Zen 2/Epyc 2's architecture turns out latency wise.
(Regarding lack of editing, a time window for fixing typos would be nicer indeed. Also I'm afraid locking OPs from being edited will just ensure more throw away threads to be created.)
Agner Fog's measurements from Microarchitectures (on page 157).First I don't know where you get the numbers from.
We were talking about uniformity of latency. That the ring bus is not uniform. And that the mesh that replaces the ring bus is significantly more uniform but starts at a latency close to the ring bus' worst case.Intra CCX numbers are a lot better than that.
Agner Fog's measurements from Microarchitectures (on page 157).
The amazing @kokhua predicts on Twitter that there is no L4$. I believe him.
On these forums it seemed the opposite to me. He infers some sort of L4 based on the larger than expected size of the IO die. Where is the tweet?
ROME I/O die is ~420 mm^2, so balance is 265 mm^2. In Zeppelin, the controllers/random logic and glue amount to ~68 mm^2. Multiplying by 4 gives 272 mm^2, more then the balance 265 mm^2. Based on this alone, I think we can conclude that there is no L4 cache.
why didn't AMD make their Rome chiplet design like this:
But if over 150mm² Matisse would be just fine for desktop then why wouldn't about the same size chiplet design be chosen for server CPU?
If they used 16C chiplets, as per your speculative suggestion, then it wouldn't look all that pretty for AM4.
Yields.
Why make an inferior choice if you don't have to? If they want to avoid the extra latency of an IO die, they have to make Matisse single die. This makes sense for desktop. This then constrains them to ~150mm^2 die, and they just have to eat the loss this causes them.
7nm yields are good enough to make chips, but they are not at full mature levels yet. Actual, current yield numbers are trade secrets and the curve is usually only fully revealed after the yields are mature, so we have to guess.
(264*2)/667= 0.79. Moving to 16-core CCD means giving up 20% of your product. Smaller is always better. You never ask, "why didn't they just double it". The reason is always obvious. It costs a lot of money to move to bigger die. Even if they are using a bigger die for products that need it, they still want the smallest possible die for the product that don't.
The more interesting question is, why didn't they just halve it? Why not use 16x4 core dies? That would buy them another 10% of yield. I think the reason for that is that CCX is 8 cores now.
That said I don't expect the whole package to be much more expensive for AMD then Summit Ridge. But you aren't doing that with a 150-180mm core chiplet and a sizeable 14nm IO die.
Current running theory is that the Navi APU will be set up as 2 chiplets and an IO chip. So on top of my personal theory that Ryzen 3k is going to be single Chiplet / Single IO and then Zen 3 will be Dual chiplet single IO (moving standard desktop to 16 cores). AMD will need space and affordability on the APU's to include a 2 chiplets and an IO for $100-$200 ASP.
As one who expected a good chance of an interposer based solution, I was conscious of an increased cost for this choice.
Still they want to go with Vega 20 (336 mm²) first... But it's true that it's not their bread an butter and they really want to do well with server CPUs. Therefore it's much more important design choice what they did with their EPYC line and they can be much more risky with their Radeon Instinct line. That's actually only product which competes very well with nVidia's current offerings (in highest end).
Multiple chiplets on an organic base are not substantially more expensive than one monolithic chip. There is a little bit of extra cost in packaging and testing, but that is probably less than the savings. The biggest reason to go monolithic on desktop is DRAM latency -- since they are using lines on organic package, they will have to use SerDes, and that always costs a few cycles. For servers, the unified memory space is worth losing a little bit on latency, but on desktop, especially in games, it still hurts.
Even given that, I honestly think that it's quite unlikely that there would be 3 separate 7nm Zen2 dies. Aside from the chiplet for EPYC and TR, I think that an APU die is possible, but I honestly think it would be unlikely that there would be a separate one for >8 core Ryzen. Either entire non-HEDT market is served from the APU chip, or there is a separate IO chip that gets paired with 2 cpu chiplets.