Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Fjodor2001

Diamond Member
Feb 6, 2010
3,867
336
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People have to justify their purchases.

You mean they'd rather have an Intel CPU, but buy an AMD CPU anyway, and then complain about Intel having higher power consumption to justify purchasing AMD anyway?

Marketing.
They're niche but winning the halo is nice.
OK, so AMD is only making AM5 CPUs with more than 8C for marketing purpose. Right.

Then why is the top selling AM5 CPUs on Newegg occupied by 12-16C CPUs on position 4-7?



YES!
Always were, are, and will be!
The chip cost there is tiny relative to machine total BOM.
The M2 Max CPU cost is tiny on MacBook? Certainly not. And they use M2 Max on both cheap and expensive MacBooks. b.L makes sense on all of them.
You can pay for that in desktop.
You're contradicting yourself. You said consumers can pay for expensive CPUs on desktop so they do not have to use b.L CPUs, yet there are a huge amount of cheap/povery AMD desktops on the market. Why is AMD not using b.L for those cheap AMD desktops? Does not compute.
 
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adroc_thurston

Platinum Member
Jul 2, 2023
2,819
4,158
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You mean they'd rather have an Intel CPU, but buy an AMD CPU anyway, and then complain about Intel having higher power consumption to justify purchasing AMD anyway
Whatever floats their boat.
OK, so AMD is only making AM5 CPUs with more than 8C for marketing purpose. Right.
Absolutely.
Then why is the top selling AM5 CPUs on Newegg occupied by 12-16C CPUs on position 4-7?
People like having the biggest stick even if they don't need it.
The M2 Max CPU cost is tiny on MacBook?
Max is a speciality part and it's ASP is still tiny if it was a merchant laptop chip.
You said consumers can pay for expensive CPUs on desktop so they do not have to use b.L CPUs, yet there are a huge amount of cheap/povery AMD desktops on the market
Desktop ASP is $250 for AMD.
Laptop ASP is like $100.
Hope that makes it all clearer.
 

Abwx

Lifer
Apr 2, 2011
11,104
3,780
136
They both leave retailers razor thin margins. It’s not vendor specific nor is it limited to CPU sales. Retailers have almost no margin on GPUs as well.
GPUs are not sold by AMD but by OEMs, for CPUs margin wise AMD provide better numbers for retailers, intel is known for mînimal margins left, ask those who work in this area.
 
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Joe NYC

Platinum Member
Jun 26, 2021
2,157
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That sounds good, but I want to see some tests first.
Based on the supposed memory subsystem 256-bit 8500mbps LPDDR5x + 32MB cache, it is comparable to what N33 has and memory is shared with the CPU.

Then N3.

Maybe N3 for the GPU part. But if that par is also doing I/O, that would mean lot of that non-scalable I/O, SRAM, analog on N3...

For 4060Ti level of performance, It would need ~2.5GHz.
For 7700XT level of performance, It would need ~3GHz.
I am not taking into account the memory subsystem.

For an all-rounder like Strix Halo, I am surprised they didn't save some space by using 8 Zen5 and 8 Zen5c cores, but with >100W TDP maybe It wasn't worth It.

Zen 5 is a separate chiplet, so saving of space is not applicable as it would to a monolithic APU. You either include one or 2 Zen 5 chiplets for 8 or 16 cores.
 

jamescox

Senior member
Nov 11, 2009
637
1,103
136
SoIC is now both bump- and bumpless-3D.
In any case, MI300 is SoIC-X 9um for everything.
Seems like it should be named something else if it uses bumps.

Yea.

No.

Yes.

No, Zen5 brings quite literally 0 system design changes for parts not named Strix-Halo.

Man you're kinda-sorta-almost getting it.
Wrong focus though.

Well, 3D stacking is decidedly not mainstream, yes.
Stix Halo looks more like just using desktop chiplets in mobile, except with big gpu + infinity cache in IO die. It doesn't seem like it brings much in the way of system design changes except for the on package memory. I was thinking they would use infinity fabric fan out (as used for the GCD <-> MCD connection in gpus; not sure what they are calling it) rather than stacking for mainstream parts. I guess that isn't coming with Zen 5.

I thought that they might do something similar to Apple, perhaps with APUs that could be connected together for high end parts. That would require higher speed interconnect thant GMI though. I also thought about an APU with a GMI link to add extra cpu cores. That seems like a good solution to use low power integrated cores with the option of powering up an external chiplet under high demand or when plugged in. The rumored device with all cores on external chiplets doesn't seem like it can get down to really low power operation.
 

adroc_thurston

Platinum Member
Jul 2, 2023
2,819
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Seems like it should be named something else if it uses bumps.
Well it's TSMC's name for trve 3D stacking so it's 3D whether it's bumped or bumpless.
Stix Halo looks more like just using desktop chiplets in mobile
No.
It doesn't seem like it brings much in the way of system design changes except for the on package memory.
MALL is the system design change!
I was thinking they would use infinity fabric fan out
YES.
Yes they do.
It's literally a sign of what's to come.
perhaps with APUs that could be connected together for high end parts
APUs, no.
GPUs? Well you've seen the Colossus.
That would require higher speed interconnect thant GMI though. I also thought about an APU with a GMI link to add extra cpu cores.
GMI is on its way out, forget about it.
The rumored device with all cores on external chiplets doesn't seem like it can get down to really low power operation.
USR over 2.5D is cheapo-cheapo and a 32MB MALL can cover for quite a lot of mem requests.
 

TESKATLIPOKA

Platinum Member
May 1, 2020
2,381
2,879
136
Yea but you get more SLC bandwidth.
Interesting. So for 32MB they bumped the speed or added more channels.
Ahhh taping out another CCD with only 8 Zen5c is a major effort since it's a totally new floorplan and not a low-effort IFOP replacement.
True. I keep forgeting Strix Halo won't be monolith, that is Strix Point.
So Strix Halo should consist of 2 CCDs, 1 IOD, maybe 1-2 GCD?, separate MALL with memory controller in MCDs or as part of IOD?
 
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DisEnchantment

Golden Member
Mar 3, 2017
1,626
5,910
136
Quite odd if Strix Halo, the precursor of what is to come with Zen 6 lineup with all the modular chiplet tech, new packaging concepts etc. to not go with an RDNA4 chiplet if it launches late next year?
 

JustViewing

Member
Aug 17, 2022
139
239
76
Whatever floats their boat.

Absolutely.

People like having the biggest stick even if they don't need it.
Ah, I wish known that before buying, could have saved me some money.
Nah, I actually need more cores, that is why bought it, not because I want to show off. That is exactly the reason I want more than 16 cores for Zen5.
 

adroc_thurston

Platinum Member
Jul 2, 2023
2,819
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Quite odd if Strix Halo, the precursor of what is to come with Zen 6 lineup with all the modular chiplet tech, new packaging concepts etc. to not go with an RDNA4 chiplet if it launches late next year?
APUs have more rigid schedules so RDNA4 wasn't quite an option when STX-halo started.
Nah, I actually need more cores
Good for you.
Storm Peak is waiting.
That is exactly the reason I want more than 16 cores for Zen5.
Zen5 TR will be very late, unfortunately.
 

Joe NYC

Platinum Member
Jun 26, 2021
2,157
2,739
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Quite odd if Strix Halo, the precursor of what is to come with Zen 6 lineup with all the modular chiplet tech, new packaging concepts etc. to not go with an RDNA4 chiplet if it launches late next year?

It probably makes sense to launch the new generation on the main product before creating derivative products. In case of RDNA, the main product is the dGPU.

The Strix products will use the same generation of RDNA 3 - which will apparently be the 3.5. And even if Strix Halo is for later in 202, the first Strix products will likely launch in first part of 2024.
 

TESKATLIPOKA

Platinum Member
May 1, 2020
2,381
2,879
136
Quite odd if Strix Halo, the precursor of what is to come with Zen 6 lineup with all the modular chiplet tech, new packaging concepts etc. to not go with an RDNA4 chiplet if it launches late next year?
This is not really surprising. It already happened In the past with APUs. Cezanne used Zen3 + Vega IGP despite RDNA being already released.
 
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