I wish but alas.and I think he is full of it. Or perhaps just misinformed
I wish but alas.
Ehhh, if AMD could keep RDNA 3's underwhelming performance under wraps, they could keep Zen 5 under wraps.Guess we'll find out come March or so. Hell it'd be nice to have an insider. I just don't buy it. AMD has been too good recently at keeping things wrapped up.
Same thought here but I was just refraining from pointing it out since it is not explicitly mentioned but also seems ambitiousI think it's fairly clear what is meant here. Currently, all Zen CPUs have 32-byte data paths between caches. When there is a miss to a higher cache level, it takes two cycles to do a fill, 32 bytes at a time. I think 64 Byte fills means that this path has been widened to full cache line width, at least between L2 and L1.
Ehhh, if AMD could keep RDNA 3's underwhelming performance under wraps, they could keep Zen 5 under wraps.
Thats one bad example. But I just saw the benchmark where 2 Genoa 48 core beat both a dual 56 core and dual 60 core Intel setup, their best. And Zen 5 promises to be even better. Not to mention, no test of Genoa-x or Bergamo. Yes, these are all Zen 4 but virtually nobody ir arguing that en 5 will be at LEAST 15% better, maybe as much as 30%.Ehhh, if AMD could keep RDNA 3's underwhelming performance under wraps, they could keep Zen 5 under wraps.
I think AMD leaks like a sieve. I don’t think RDNA3 was kept a secret but just hyped beyond belief by the usual suspects to where it was always going to underperform relative to expectations.Ehhh, if AMD could keep RDNA 3's underwhelming performance under wraps, they could keep Zen 5 under wraps.
No lol, they're not Intel.I think AMD leaks like a sieve
It underperformed their FAD'22 slides.I don’t think RDNA3 was kept a secret but just hyped beyond belief by the usual suspects to where it was always going to underperform relative to expectations.
That's something that's been troubling me. How could they only know the performance failure so late? Any clues?No lol, they're not Intel.
It underperformed their FAD'22 slides.
Lying to the investors is bad mkaay.
All models are wrong. Some are useful - George BoxThat's something that's been troubling me. How could they only know the performance failure so late? Any clues?
So what price do you expect instead for 8950X, assuming only 16C and only 15% perf increase?
Just because @adroc_thurston mentioned $999, doesn't mean he is right.But I could be wrong, and Zen5 will actually be as bad as mentioned in my previous recent posts (only 15% perf increase, and price bump to around $999). However then I’ll definetely go for Zen4 instead, which would be much better bang for the buck.
Just because @adroc_thurston mentioned $999, doesn't mean he is right.
I don't think price is set at this point.
15% increase at $999 price point is nonsense.
MSRP:
5950X -> $799
7950X(3D) -> $699
7950X saw a 32% increase in performance(TPU) compared to the predecessor, yet It cost less money. Of course this reduction in cost was most likely due to high platform cost vs Intel platform.
I won't guess Zen5 performance, because I don't know.
What I know is that they have to set the price to be competitive in perf/$ not just against Intel but also Zen4.
I assume they've ID'd the uArch or implementation issues but those couldn't be fixed with a stepping and needed retapes (which is a lot of effort and money).How could they only know the performance failure so late?
Vendors always clearly communicate platform-level pricing creep before launch.Price is almost always set just before launch
Price is almost always set just before launch. Another reason I don't believe a thing he says.
This sentence makes no sense.Given that Turin is unfortunate amount more expensive than Genoa no reason to think GNR won't be (for slightly different reasons tho).
Yield problems for Intel 3?(for slightly different reasons tho).
The slides don't mention clock anywhereWell, I said 15% perf. So that would be the net of any IPC increase and frequency reduction.
Or are you suggesting 10-15% IPC increase, with frequency reduction of X %, resulting in 10-15% IPC - X% frequency reduction, resulting in 10-15% - X% net performance improvement for Zen5 over Zen4?
Here's the vodNo lol, they're not Intel.
It underperformed their FAD'22 slides.
Lying to the investors is bad mkaay.
Regardless of price difference?
The 7950X3D is around $650 now, and will likely be $500-600 by BF. Meanwhile some in this thread have suggested the non-X3D successor 8950X will be around $999. Now if 8950X is only 15% faster than 7950X3D, would you still be willing to wait ~6 months for 8950X and pay close to double the price for it compared to 7950X3D?
The price $999 for 16C 8950X was mentioned by adroc_thurston, whom some here apparently hail as an AMD insider, whether accurate or not. If not accurate, I guess that puts his insider status into question.
Probably referring to RDNA 3's projected performance/watt uplift being stated as >50% starting at 1:05:30.Here's the vodCan't find what you are talking about anywhere
And if you compare a 6950XT with a 7900XTX it is only about 28% (using TDP values and relative speed from TPU)Probably referring to RDNA 3's projected performance/watt uplift being stated as >50% starting at 1:05:30.
No idea how things are with the zen4 3d, but on my 5800x3d I see kinda the opposite, i.e. the cores are running at L3 clock speed, since the L3 process/infrastructure limitations come into effect way before those for the cores, so their effective clocks almost always follow the current L3 Fmax.Since L3 runs at core clock it is going to be really fast if width is 2x but it will burn more power. Interesting thoughts to be had for V cache here.
Same thought here but I was just refraining from pointing it out since it is not explicitly mentioned but also seems ambitious
L2 evictions are 32B/cycle or 2 cycles for each cache line.
So it is quite intriguing for a possibility of evictions as each cache line per cycle.
For me as a non-native english speaker, it's not quite clear how one should interpret "going to" at 1:06:10, inProbably referring to RDNA 3's projected performance/watt uplift being stated as >50% starting at 1:05:30.
Well the slide did mention 4 loads/ 2 stores per cycle, which would imply 4x 256 bit (AVX2) or 2x512bit (AVX512). If the core can sustain it, that would mean it doubles the FP throughput versus Genoa.The first Intel's CPU that had 64 byte path from L2 was Haswell. While "sustained" BW was not that great, the path was 64 bytes.
So i think 99.99% that AMD's L2 will have 64 byte / cycle width, it's long overdue.
L3 having that wide path would make little sense tho as AMD's L3 is already excellent and X3D variants even more so.
The real shenanigans come with how many "ports" L1 will have and how many 256bit loads / stores they will support per cycle.