Fwiw, 8 Gen 3 is rumored to be 3.2GHz at the baseline. So Apple will have a 15% clock advantage. Adjusting them for 3.2GHz, the A17 is at about 2400-2500.That comparison is not fair.
Snapdragon 865 was released in 2019 (november 15) vs 2019 (september 10) for apple's A13.
Snapdragon 8 gen 2 was released 2022 (november 15) vs 2023 (september 26) for apple's A17.
For a more accurate comparison you need to wait until november for the Snapdragon 8 gen 3.
I'm estimating 2200-2300 score (IPC + high freq increase), that would means the A17 is 'just' 28-30% faster.
Apple does not retain its perf advantages, apple cores are stagnant.
Lmfao don’t read into that. Vince also hypes up the L3 gains and a lot of that is probably dependent on what you’re doing which for the average user besides gaming you are not getting “such huge gains”. The “faster” is also true but at a particular wattage and some benchmark and we know Intel’s aren’t meaningful there anyways — Arm is just taking the flipside of that almost certainly e.g. capping the TDP. It’s not new that a jacked out X3 — especially X4 now — could make a good laptop chip.GUYS THIS IS INSANE!
So they mention how Cortex X3 with 16 MB L3 is 34% faster than Intel i7 1260P. That is incredible.
What's your thoughts on this thread guys? (Read the entire comment chain)
If increasing the L3 cache from 8 MB to 16 MB can bring such huge gains, why aren't mobile SoC vendors doing it? They could massively close the gap with Apple.
Yeah I was a bit skeptical, hence why I posted here to see a different viewpoint.Lmfao don’t read into that. Vince also hypes up the L3 gains and a lot of that is probably dependent on what you’re doing which for the average user besides gaming you are not getting “such huge gains”. The “faster” is also true but at a particular wattage and some benchmark and we know Intel’s aren’t meaningful there anyways — Arm is just taking the flipside of that almost certainly e.g. capping the TDP. It’s not new that a jacked out X3 — especially X4 now — could make a good laptop chip.
But there would still be a minor improvement in performance, would it not? If we are measuring by benchmarks like Geebench 6, could you estimate the % performance gain going from 8 MB to 16 MB?The main difference L3 would make is in terms of power, not general performance on a smartphone. The gap is already closing with Apple to some extent anyways btw, but ultimately Apple do have better cores with larger L1s, massive L2s that shift their memory hierarchy down a set. It’s a better design for the purpose (great performance and low power) but costly.
More likely die area and therefore profitability from more SoC's for any given wafer regardless of yield.Question: Is reduced yield (apart from cost), the reason why Android SoCs cheap out on the cache?
I came across someone who said putting more SRAM on the due reduces the overall yield.
There are also power budgets to keep in mind, while SRAM doesn't require refresh cycles like DRAM they are all active transistors meaning they all leak. You can power gate a CPU core that's not in use or even parts of a CPU core that is in use, but you can't power gate SRAM unless you disable blocks of cache and run with less (and if you do that very often why did you increase your cache size in the first place?)
In addition to that leakage power, the more you use SRAM the more power it draws. So sure using a larger cache might increase performance but in doing so it also burns more power, leaving less for your CPU, GPU, etc. It isn't as simple as "I'll pay 10% more for a 10% bigger die that's got lots of cache and get more performance with no downside". Everything has tradeoffs in the CPU design world.
You also need a very good design to be able to get low latency with larger cache sizes. The whole reason why we have separate L1 and L2 caches is because there is a trade-off between capacity and latency- the larger a cache, the longer it takes to search. L1 is blazing fast but low capacity, L2 is larger but noticeably slower.Question: Is reduced yield (apart from cost), the reason why Android SoCs cheap out on the cache?
I came across someone who said putting more SRAM on the die reduces the overall yield.
You also need a very good design to be able to get low latency with larger cache sizes. The whole reason why we have separate L1 and L2 caches is because there is a trade-off between capacity and latency- the larger a cache, the longer it takes to search. L1 is blazing fast but low capacity, L2 is larger but noticeably slower.
The fact that Apple can get such good latencies with large L1 caches is a testament to the talent of their CPU design teams. Zen 3 cores have a total of 64KB L1, but Apple M1 cores have 288KB L1. Cache design is hard.
That's old A510, The one used with A715 is refreshed one.
Which is measly 5% more efficient, according to ARM themselves.That's old A510, The one used with A715 is refreshed one.
By 'memory', you mean RAM ?The Dimensity also features more advanced memory, leading to (according to MediaTek) 17% faster transfer speeds and 15% lower latency - in addition to (according to Samsung) 20% lower power consumption.
But shouldn't the merged core design theoretically be more efficient?The merged core design also shares the NEON SIMD engine between pairs of cores, the bandwidth of which can additionally be halved.
So, basically, the two A510 "systems" are *completely* different.
By 'memory', you mean RAM ?
So yes the Mediatek *supports* LPDDR5X but the phone in question should have it to take advantage of the gains you mentioned.
But shouldn't the merged core design theoretically be more efficient?
In real Life A715+A510 combo has really good battery life Compare to A710+A510. Most Reviewers don't have standardized review for battery life, the only one I can find now is PhonearenaWhich is measly 5% more efficient, according to ARM themselves.
🤣
Are these both TSMC N4?View attachment 87428View attachment 87429
Snapdragon 8 Gen 2 : 118.4 mm^2
Dimensity 9200/9200+** : 120.5 mm^2
The tweet attached says SD8G2 is N4 and D9200 is N4P.A
Are these both TSMC N4?
Slightly unrelated question, do different companies that use ARM IP customize the layout of the same core for better perf or efficiency? Because the A715 in the snapdragon chip doesnt look like the A715 in the dimensity chipThe tweet attached says SD8G2 is N4 and D9200 is N4P.
Which... sounds kinda dubious.
Slightly unrelated question, do different companies that use ARM IP customize the layout of the same core for better perf or efficiency? Because the A715 in the snapdragon chip doesnt look like the A715 in the dimensity chip