I think the ST IPC is not the same. But the inter core communication is somehow better between the c cores.How can a core with halved L3 have the same IPC?
Level 3 cache is not part of the core. It's part of the core complex.How can a core with halved L3 have the same IPC? Has L3 suddenly become irrelevant?
But they have the same IPC in the Zen 4 generation (if the amount of cache is the same, if memory interface is the same, etc.). *Maybe* they won't have the same floating point IPC in the Zen 5 generation anymore, but I guess integer IPC is still the same.even though each core has lower IPC than a fat core,
That'd be a property of the core complex again, not of the cores.But the inter core communication is somehow better between the c cores.
So the only difference is that the c cores can't be clocked higher and they are more power optimized? That raises an interesting question. Does the fat core need more circuitry to sustain higher frequency? Or are the higher frequency transistors taking up more space (maybe spread further apart from each other to keep heat down)?But they have the same IPC in the Zen 4 generation
The Zen 4 "dense" cores are only area optimized (and the major repercussion of it is their lower f_max), not power optimized.So the only difference is that the c cores can't be clocked higher and they are more power optimized?
(If you recall spectacular perf/W of Bergamo, even better than Genoa in fully scalable compute-bound workloads, then that's because Bergamo operates even nearer the most power efficient f-V spot then Genoa and has got even more cores on top of the same IOD and RAM foundation as Genoa. Bergamo must work nearer this sweet spot than Genoa simply because Bergamo's power budget per core is lower than Genoa's.)
A bit pedantic, but whatever.Level 3 cache is not part of the core. It's part of the core complex.
In mobile parts, AMD has provided less level 3 cache compared to desktop and server parts before "dense" a.k.a. "cloud-native" cores were introduced.
In post #5,522, it was not stated what amount of cache the 8 core comparison part should have.
In the Zen4 gen, the Zen4c have 1/2 L3 as full Zen4, and AMD still claims same IPC, with no disclaimers as you have inserted, which makes no sense. How you claim (if the cache amount is the same), when it can't be, as they're 2 unique designs, with many, but not all elements shared.But they have the same IPC in the Zen 4 generation (if the amount of cache is the same, if memory interface is the same, etc.). *Maybe* they won't have the same floating point IPC in the Zen 5 generation anymore, but I guess integer IPC is still the same.
Yes they are, literally lower Cac.not power optimized.
No they both operate about their optimum V/f spots.even better than Genoa in fully scalable compute-bound workloads, then that's because Bergamo operates even nearer the most power efficient f-V spot then Genoa and has got even more cores on top of the same IOD and RAM foundation as Genoa.
It’s only going to be a few % lower. Not enough to undo the IPC gains. But in mobile applications the standard Z5 core gets half the normal L3 anyways so I bet Z5c is actually comparable.This is something I've struggled to understand. How can a core with halved L3 have the same IPC? Has L3 suddenly become irrelevant?
What is the rumored total L3, still 16MB?It’s only going to be a few % lower. Not enough to undo the IPC gains. But in mobile applications the standard Z5 core gets half the normal L3 anyways so I bet Z5c is actually comparable.
What is the rumored total L3, still 16MB?
Zen5c should support 16 core CCX, so is it shared between 12 cores or partitioned to a 4x "big" core CCX and a 8x"small" core one?
STX
TSMC N4P 225mm²
4c Zen 5 L3: 16 MB L2: 4 MB
8c Zen 5C L3: 16 MB L2: 8 MB
8 WGP RDNA3+
64 AIE tile
DDR5-5600 / LPDDR5X-8533
28-35+ W
This is something I've struggled to understand. How can a core with halved L3 have the same IPC? Has L3 suddenly become irrelevant?
Because most likely that IPC is measured at 1T, so It doesn't matter If you use Zen4(5) or Zen4(5)c core, you still have the whole L3 for that single core.In the Zen4 gen, the Zen4c have 1/2 L3 as full Zen4, and AMD still claims same IPC, with no disclaimers as you have inserted, which makes no sense. How you claim (if the cache amount is the same), when it can't be, as they're 2 unique designs, with many, but not all elements shared.
Ok, that makes a lot of sense.Because most likely that IPC is measured at 1T, so It doesn't matter If you use Zen4(5) or Zen4(5)c core, you still have the whole L3 for that single core.
BTW, I question If L3 is really partitioned between standard and dense cores.
This is PHX2 and L3 doesn't look like It's separated physically.
I think It's not separated at all. Just the amount is 16MB for 12 cores.
Got corrected immediately to 8MB L3 for the ZEN5c CCX. So the 4 ZEN5 Cores get 16MB L3, the 8 ZEN5c Cores get 8MB L3.
Hmm, if that is correction, then total L3 cache of STX is 24MB....50% larger than PHXGot corrected immediately to 8MB L3 for the ZEN5c CCX. So the 4 ZEN5 Cores get 16MB L3, the 8 ZEN5c Cores get 8MB L3.
While the physical design differs, the microarchitecture — i.e. frontend, execution units and so forth, and the resulting execution width and instruction latencies — is exactly the same (from what is publicly known, and there are no indications to the contrary). And I should rather have said: "But they have the same IPC in the Zen 4 generation (if the amount of cache is the same, if memory interface is the same, or if the present amount of cache is sufficient for the considered workload)."In the Zen4 gen, the Zen4c have 1/2 L3 as full Zen4, and AMD still claims same IPC, with no disclaimers as you have inserted, which makes no sense. How you claim (if the cache amount is the same), when it can't be, as they're 2 unique designs, with many, but not all elements shared.
In the Zen4 gen, the Zen4c have 1/2 L3 as full Zen4
I don't think so. First, such a product would need to exist.So will Strix Boind have an LLC ?
The Zen 4 "dense" cores are only area optimized (and the major repercussion of it is their lower f_max), not power optimized.
OK, what I claimed was incorrect; not sure why I said so. (Zen 4c's different physical design does shave off power consumption additionally, beyond what just a lower average operating frequency brings.) Kai Troester, Zen 4 lead architect, phrased it this way: "What we did to create Zen 4c is take the Zen 4 functional design, which keeps IPC and features identical [...] We targeted a design frequency optimized for cloud servers, and with that lower frequency we were able to significantly reduce the area of the core. And that smaller area led to tremendous increase in power efficiencies, allowing us to provide 33 % more cores in the same power envelope at high frequency and IPC." (Source: Hot Chips 2023 CPU 1 session video) — Is there something more detailed published anywhere?Yes they are, literally lower Cac.
LLC stands for Last Level Cache. So if a chip has no L4$, L3$ is the LLC. If no L3$, L2$ is it, and so on. So since Strix Point definitely has cache the answer is yes? I'm not sure what you actually wanted to know. Maybe if LLC is shared between CPU and iGPU? (That be a no.)So will Strix Boind have an LLC ?
Edit: Typo. Correction: "Strix Point"
Yes. That. LLC in the form of an SLC.Maybe if LLC is shared between CPU and iGPU? (That be a no.)
Yes. That. LLC in the form of an SLC.
Is that specifically a characteristic of RDNA?The hit rate from the iGPU is terrible, so having it pollute the same cache that the processor uses is not usually a good tradeoff.