No, as usual you understand very little of how process nodes can be tweaked to account for target PPA which is variable based on the design under consideration.
An A78 shrunk from N5 to N4 will certainly not be the same as a Zen 5 shrunk from N5 to N4 as they are vastly different PPA targets.
Power-frequency scaling is dependent on the design. A node to node shrink of an x86 core will give different PPA than a node to node shrink of an arm core.I guess that it s you who dont understand, when you shrink a core to a smaller but comparable process then it s just the curve that is translated in a graph, FI if a Cortex fabbed with N5 run a 2GHz and consume 0.25W then a shrink with a process that use 20% lower power/isofrequency will yield 0.2W/2GHz, likewise if a X86 core use 20W/5GHz then with the new process it will use 16W/5GHz.
Power-frequency scaling is dependent on the design. A node to node shrink of an x86 core will give different PPA than a node to node shrink of an arm core.
So are we expecting MT perf increase to be worse than ST perf increase, since for MT it will hit the power limit preventing further perf increase?IPC isn't free, you're paying in area and power.
A14 = 11.8 billion xtors 88 mm2 die size = 134 MTr/mm2 (N5)So you are saying that TSMC cant guarantee those numbers with anything other than their tests chips..?..
That's how it always goes, kiddo!So are we expecting MT perf increase to be worse than ST perf increase
Socket-level per-thread perf bump is always lower than the 1t bump.since for MT it will hit the power limit preventing further perf increase?
So what MT perf increase can be expected, going from 7950X or 7950X3D to corresponding Zen5 16C equivalents?That's how it always goes, kiddo!
Socket-level per-thread perf bump is always lower than the 1t bump.
A14 = 11.8 billion xtors 88 mm2 die size = 134 MTr/mm2 (N5)
A13 = 8.5 billion xtors 99 mm^2 die size = 85.6 MTr/mm2 (N7P)View attachment 96050
Density increase = 1.57x
Which if my math is not wrong is lesser than 1.8x.
A14 = 11.8 billion xtors 88 mm2 die size = 134 MTr/mm2 (N5)
A13 = 8.5 billion xtors 99 mm^2 die size = 85.6 MTr/mm2 (N7P)View attachment 96050
Density increase = 1.57x
Which if my math is not wrong is lesser than 1.8x.
If that’s a legit score that’d be a bad result since a 7950X will regularly score 3000-3200 and a 13900K will usually get a score in the range of 3100-3300.Unhappy with Cinebench speculation?
Then let me show you some happy data?
9950X
GeekBench 6
single 3628 more than 23868
GeekBench 5
single 2715 more than 27712
(Only test data, does not represent the final result)
A14 big core = 2.1 mm2You didn't read the table you posted. It says "logic area", while a real SoC includes transistors other than logic such as cache (leaving out the other categories that also aren't logic but maybe don't scale as poorly as cache)
Yes. A13 and A14 are almost the same architecture as far as the CPU is concerned. As demonstrated above, the logic density increase is nowhere near what TSMC advertises - because they typically have an old arm core as the reference.We re talking of PPA, you are just changing the goal posts, as if density has something to do with PPA, it took you all this time to find such a poor straw.?..
If that’s a legit score that’d be a bad result since a 7950X will regularly score 3000-3200 and a 13900K will usually get a score in the range of 3100-3300.
A 30% 1T increase would mean a score >=4000.
So 40+ % perf increase in that benchmark, but only 3628/3100 => ~20 % in GB6 compared to 7950X?Pretty sure the 40% refers to spec int 2017 ST only.
Which should correlate well with Geekbench 6 1T.Pretty sure the 40% refers to spec int 2017 ST only.
So 40+ % perf increase in that benchmark, but only 3628/3100 => ~20 % in GB6 compared to 7950X?
And also, if 13900K is 3300 in GB6 like @H433x0n said it would mean 9950X is only ~10% better than that.
Which should correlate well with Geekbench 6 1T.
What I'm implying is that SPECint_rate_2017 1T and Geekbench 6 ST correlating 1:1 means that either 40% performance gain over Zen 4 is untrue or that the ES leak showing a score of 3600 in ST is made up.I am just pointing out a factual statement, if it should or should not correlate is of no relevance to ensuring the accuracy of the claim which was always centred around SIR2017 ST, whether that be the 32% IPC claim or the 40% performance claim.
What I can see happening by certain posters is the performance delta differing in CB / GB / CPU-Z and them using that to go see, the 40% was BS when the claim was always SIR2017 ST. If SIR2017 ST has a smaller performance bump than claimed sure, have at it but CB/ GB / CPU-Z are no the same as SIR2017 ST so don't conflate them.
So the conclusion is that 40+ % in SIR2017 ST, and ~20% vs 7950X & ~10% vs 13900K in GB6, can both be valid since what the benchmarks measure differs so much?CB/ GB / CPU-Z are no the same as SIR2017 ST so don't conflate them
You didn't read the table you posted. It says "logic area", while a real SoC includes transistors other than logic such as cache (leaving out the other categories that also aren't logic but maybe don't scale as poorly as cache)
A14 big core = 2.1 mm2
A13 big core = 2.61 mm2
Please tell me where the 1.8x logic density increase is in the actual chips?
Yes. A13 and A14 are almost the same architecture as far as the CPU is concerned. As demonstrated above, the logic density increase is nowhere near what TSMC advertises - because they typically have an old arm core as the reference.
And frequency/power claims are even more misleading. They typically refer to a simple ring oscillator, let alone a basic CPU.
It's not my problem if you are clueless, which isn't surprising.
What I'm implying is that SPECint_rate_2017 1T and Geekbench 6 ST correlating 1:1 means that either 40% performance gain over Zen 4 is untrue or that the ES leak showing a score of 3600 in ST is made up.
So the conclusion is that 40+ % in SIR2017 ST, and ~20% vs 7950X & ~10% vs 13900K in GB6, can both be valid since what the benchmarks measure differs so much?
Then the question is what benchmark to focus on. Or perhaps better look at an average of the different benchmarks, instead of just cherry-picking one of them.
This was in January 2022.Or the ES is clock / power limited in someway that would not apply to a retail unit as a 3rd option. We will know more when we get details.
This was in January 2022.
AMD demonstrates its next-gen Zen4 Ryzen 7000 CPU in Halo Infinite with all-core frequency of 5GHz - VideoCardz.com
Ryzen 7000 is hitting 5.0 GHz on all cores, claims AMD During its 2022 Product Premiere AMD demonstrated its next-gen processor with a short gameplay video. AMD not only confirmed the leaks featuring a unique AM5 CPU integrated heat spreader design but also confirmed it will be the first...videocardz.com
Zen 4 launched in September 2022.
The Zen 5 GB6 leak was from November 2023.
Given AMD's history of leaks and teasers, I don't think there is very strong evidence to believe that the ES was running at clocks very far from final targets.