Not quite but it does enable more direct IP sharing between DT and mobile or ultrathin and luggable depending on your definition.That should finally bring more modularity / re-useability to client PCs, and hopefully, faster release cycles. And maybe even a greater range of SKUs.
culled for time frame or cost/throughput/defect rate or both?Yeah it's all one thing.
That's the idea.
Not seems, that was the OG definition.
The former two iirc plus overall fanout capacity.culled for time frame or cost/throughput/defect rate or both?
I'm more interested in the extent to which AI is related to the architecture itself, rather than it being the specific compute block a-la FPGA.Strix Point Next Gen AI PC is what Papermaster is mainly hinting at
None.I'm more interested in the extent to which AI is related to the architecture itself
whatFor example, region specific ram access scheduling, or like the instruction scheduling based on occupancy or power prediction
None.
what
US10956044B2 ?
There's probably some OEMs who will try. But 16 CU + 12 Cores feels wholly inappropriate for a Handheld device.
Then again people are using these while connected at wall charger all the time and full blasting at 45W. To the point that the Handheld aspect basically lost it's meaning
You don't need hallucination machines for that.I think he thinks that AI is being used to direct the chip, like it has an AI processor to "optimize" how it should schedule and utilize resources within the chips?
Not quite but it does enable more direct IP sharing between DT and mobile or ultrathin and luggable depending on your definition.
If they do tiled HSIO, possibilities extend though.
Like a luggable core/SOC but HSIO is loaned from the premium ultrathin 28W part so it gets USB4s and all.
Dunno if they're gonna do that, though.
You don't need it, but they did use a perceptron for branch prediction at one point for Zen2 or something?You don't need hallucination machines for that.
BobcatYou don't need it, but they did use a perceptron for branch prediction at one point for Zen2 or something?
They still do, two-level overriding BP is still very much AMD's favourite gimmick.You don't need it, but they did use a perceptron for branch prediction at one point for Zen2 or something?
Oh, I thought that something called a TAGE predictor replaced it.They still do, two-level overriding BP is still very much AMD's favourite gimmick.
Augmented.Oh, I thought that something called a TAGE predictor replaced it.
Kind of.I think he thinks that AI is being used to direct the chip, like it has an AI processor to "optimize" how it should schedule and utilize resources within the chips?
Well, I didn't claim it necessarily has, I just gave a bad example, but in general you got the idea correctly.What does that have to do with AI?
The above method may be implemented for each of the cores, from the first core to the last core (also referred to herein as “core N”), as suitable. The processor cores may be evaluated for voltage change or “looped” by a smart firmware (that is, firmware made intelligent with advanced computing capability such as artificial intelligent or machine learning, for example) or any suitable algorithm to facilitate repeating the above process to calculate a new voltage value for each of the cores.
Problem is, from the few reviews so far, MTL-U = RPL-U. Even in battery life (Against RPL-U), it's hit or miss depending on the OEM implementation. Here, Bionic claims that the move to Intel 3 will yield 10% PPW improvement over Intel 4 Compute Tile. But is that enough for OEMs to choose ARL-U over the cheaper RPL-U?
Good points! If OEMs can lower platform costs to offset the SoC cost, it can allow them to offer it at attractive price points.they have the option of setting lower PL values than with Meteor Lake and achieving the same performance. That lets them skimp on cooling and battery. It might be enough to drive BoM down and make for attractive budget machines.
Right. This is where I question if we'll see proper, Intel like, volume for ARL-U. By 2025, the majority of their product stack will be using tiled designs and will depend on the level of packaging volume they can do.Fighting against that will be the inherent costs associated with packaging.
Yes. Still shipping RPL-U and also RPL-H as budget alternatives over ARL-U/HX.Also is Intel even going to be shipping Raptor Lake-U by that point?
Intel choice for a 5 tiles design with ARL / MTL certainly was...something. It obviously drives up their costs and limits how fast they can ship these. When faced against a simpler, monolithic competitor, Intel can't properly answer it unless they slash their margins once again (They can't).In any case the product won't have compelling performance for end users, certainly not when faced with Kraken.
I don't know much about panther lake. It will have to be an incredible uplift against arrow lake to get near AMD's zen 5 lineup. What's known about it?Good points! If OEMs can lower platform costs to offset the SoC cost, it can allow them to offer it at attractive price points.
Right. This is where I question if we'll see proper, Intel like, volume for ARL-U. By 2025, the majority of their product stack will be using tiled designs and will depend on the level of packaging volume they can do.
Yes. Still shipping RPL-U and also RPL-H as budget alternatives over ARL-U/HX.
Intel choice for a 5 tiles design with ARL / MTL certainly was...something. It obviously drives up their costs and limits how fast they can ship these. When faced against a simpler, monolithic competitor, Intel can't properly answer it unless they slash their margins once again (They can't).
If I were Gelsinger, I would be fast-tracking Panther Lake in 2025 as fast as possible. It's a much more sane design, it uses their own foundry so to reduce dependency on external and should be way more competitive with AMD across the stock, from U to H. A release of PTL in Summer 2025, with it replacing the expensive ARL designs, would to wonders to clean up Intel line-up.
It's not a big uplift over ARL, so it won't match Zen 5. But it will clean up MTL/ARL tile design mess with a much simpler tile design.I don't know much about panther lake. It will have to be an incredible uplift against arrow lake to get near AMD's zen 5 lineup. What's known about it?
Do you mean they will be low ? or high ? or something else ?View attachment 98291
I fear for Zen 5 sales.
Oh, I thought that something called a TAGE predictor replaced it.
View attachment 98291
I fear for Zen 5 sales.
I love to fear for things that are going to be unchallenged in consumer and client spaces for almost a full year before the competition puts out something that will almost assuredly be underwhelming
like, Zen 5 is going to release this year - intel claims they're getting Arrow Lake out ASAP, but real competition (and real volume with intel) for Zen 5 won't be until Panther Lake.
Even if only for laptops it seems underpowered to face Zen 5, even if Strix was to use Zen 4 cores it would still be challenging for Intel given that they seem to remove HT and also due to either the sheer amount of cores in Strix or the augmented IPC relatively to Zen 4 in Kraken.Someone on Intel thread posted that Panther Lake will be 4+4+4, which sounds like a laptop chip. Not something that would challenge Zen 5 desktop.