Not exactly, the LP island is supposed to be invisible and transition seamlessly depending on the load.With a quad-core LP cluster on the SOC die, Strix Halo will have 20 cores, right? I assume Zen 6 desktop will also get LP cluster (bacause it'll share the SOC tile with Fire Range succesor, most likely), thus slightly bumping core count too.
My bet was Strix Point(4 Z5, 8 Z5c) + LP island of 4 Z5 LP cores on the SoC.With a quad-core LP cluster on the SOC die, Strix Halo will have 20 cores, right? I assume Zen 6 desktop will also get LP cluster (bacause it'll share the SOC tile with Fire Range succesor, most likely), thus slightly bumping core count too.
Halo doesn't have any Zen5c cores.My bet was Strix Point(4 Z5, 8 Z5c) + LP island of 4 Z5 LP cores on the SoC.
Why do you think it'll have 20 cores?
That's a weird choice for a mobile product...Halo doesn't have any Zen5c cores.
Sure, some pros do, but there are still people who buy the most expensive because it must be better and then use their MBP purely for office work.MBP buyers? they sort of know what they're doing, those things start at 2 kilobuck.
With a quad-core LP cluster on the SOC die, Strix Halo will have 20 cores, right? I assume Zen 6 desktop will also get LP cluster (bacause it'll share the SOC tile with Fire Range succesor, most likely), thus slightly bumping core count too.
I think it's borderline criminal that Strix Point doesn't have any LLC for the GPU. That APU will be the king of 540p rasterization I guess.Strix Scenario
- 128 bit (memory width) N6 base die with memory controllers, MALL, IO, analog
- ~20 CU GPU stacked on top ~80 mm2
Halo doesn't have any Zen5c cores.
It's always useful to put cores into higher-end nodes (good scaling for power and area).The LP cores will be on Strix Halo SoC die, which will likely be N3E.
Whether AMD migrates LP cores to N6 node - remains to be seen (unlikely) but it would be useful.
Thanks MicrosoftI think it's borderline criminal that Strix Point doesn't have any LLC for the GPU.
Lighter loads -> work is transferred to LP cores. Heavier loads -> work is transferred to real cores. Supposed to happen automatically and transparent to OS but we'll see how it works outWhy though? AMD isn't making CCDs with Zen5c?
Doesn't this mean a chop on power efficiency for lighter loads, or do LP cores actually take over the regular ones when lighter loads are detected?
Doubt it, you're never going to be bottlenecked by Zen5 with just 40 CUs of RDNA3.5I also wonder if Halo's Zen5 CCDs can take Vcache on top.
you're never going to be bottlenecked by Zen5 with just 40 CUs of RDNA3.5
That bit is obvious, but the compressed cores are supposed to be slightly more efficient in a constrained power situation, and also they're just less area.Lighter loads -> work is transferred to LP cores. Heavier loads -> work is transferred to real cores. Supposed to happen automatically and transparent to OS but we'll see how it works out
Doubt it, you're never going to be bottlenecked by Zen5 with just 40 CUs of RDNA3.5
They simply will not have designed an 8c Zen5c CCD just for such a niche product.That bit is obvious, but the compressed cores are supposed to be slightly more efficient in a constrained power situation, and also they're just less area.
I honestly find it a bit jarring that they decided to go all or nothing. I doubt that almost any workload will truly benefit from 12 Z5 cores vs 4 Z5 cores for "pure perf" and 8 Z5c for "slightly below pure perf". It's just a really strange design decision.
Will be highly interesting to see how this works out and what strategy for switching the threads over they might employ.Thanks Microsoft
Lighter loads -> work is transferred to LP cores. Heavier loads -> work is transferred to real cores. Supposed to happen automatically and transparent to OS but we'll see how it works out
Halo uses chiplets. How would you partition the APU functions using the existing chiplets as much as possible?That bit is obvious, but the compressed cores are supposed to be slightly more efficient in a constrained power situation, and also they're just less area.
I honestly find it a bit jarring that they decided to go all or nothing. I doubt that almost any workload will truly benefit from 12 Z5 cores vs 4 Z5 cores for "pure perf" and 8 Z5c for "slightly below pure perf". It's just a really strange design decision.
Thanks Microsoft
I did that too... Sometimes there is news drought, sometimes the info is too attractive. IIRC, there were cases when leaked docs were directly pasted here. Obviously you have to be superprudent in trying to judge what may be a legit informed person and what's a random forum dude making stuff up. No offense...They have also used comments from this thread to source articles.
Wait wait wait, where did the talk of LP island/LP cores in Strix (Halo) IOD came from?Thanks Microsoft
Lighter loads -> work is transferred to LP cores. Heavier loads -> work is transferred to real cores. Supposed to happen automatically and transparent to OS but we'll see how it works out
Doubt it, you're never going to be bottlenecked by Zen5 with just 40 CUs of RDNA3.5
Advanced packaging with less overhead is pretty much a given for Halo right now.I did that too... Sometimes there is news drought, sometimes the info is too attractive. IIRC, there were cases when leaked docs were directly pasted here. Obviously you have to be superprudent in trying to judge what may be a legit informed person and what's a random forum dude making stuff up. No offense...
Wait wait wait, where did the talk of LP island/LP cores in Strix (Halo) IOD came from?
Was there some leak saying that that I missed or is this just some wild seronxposting? This feature was #1 on my wishlist (that or some advanced packaging chiplet tech that would not have power overhead)...
Strix Halo (and Mac) pose a different question: "Do you really need a costly and power inefficient dGPU if iGPU can do the same job for less money and less power consumption".
Sure, some pros do, but there are still people who buy the most expensive because it must be better and then use their MBP purely for office work.
I don't have a problem with this as people can buy their computer for whatever reason, I'm just questioning how small a fraction of buyers knows the differences between an AMD, Intel, or Apple based computer.
I might be biased because I work with teenagers in a school environment though.
My guess is that 4 Zen 5 LP cores can likely do a lot, especially if they retain much of the IPC uplift over Zen 4 that the vanilla Zen 5 core enjoys. What they strip out might be the additional transistors that allows Zen 5 to clock high. Combine that with the use of TSMC N3E FinFlex and a high density library, a hypothetical Zen 5 LP that only clocks to 2.5 GHz can probably punch pretty high while sipping power in a much smaller area. Considering that MTL's LP-E cores have roughly similar IPC as Skylake (in INT, in FP it's lower), Zen 5 should have like 50% higher IPC. Those MTL LP-E cores are also clocked to 2.5 GHz but there's only 2 of them. 4 Zen 5 LP with 50% higher ST and 3x the MT as the 2 MTL LP-E cores will cover a lot of typical use scenarios.Well duh.
The real question is what will Zen 5 LP do and not do. And what will it do "well enough".
There's a world of difference between a low power core that can scroll through a document or webpage but needs to awaken the big cores on every single new tab or page load, and one that can do web/document editing and possibly also low power video decoding without awakening the rest.
I could easily see a low power islands of 4 Zen 5 LP cores that could still have enough punch to let you watch Youtube/Twitch/Netflix or browse forums or Discord as a total beatdown on the market. 10+ hours of full scrolling/viewing/handling basic tasks without a single worry about battery.
Even if you have to set some limits like say "1080p video decoding but nothing above" or set some "low power mode" in Word or Chrome, you'd have a real monster product.
And with STX Halo you'd also have a strong graphical beast for when you want to play to boot.
Dense already does that, big dawg.What they strip out might be the additional transistors that allows Zen 5 to clock high.
Doesn't even need to go that high, most industry LITTLEs are 1.8ish.a hypothetical Zen 5 LP that only clocks to 2.5 GHz
Yeah, I was trying to find it after I saw your comment. But the combined effect of reducing buffer cells due to a lower clock target + prolific use of a high density library should result in a very compact, power efficient core. There's nothing novel to this approach, but it will be interesting to see how much small AMD got it down to.Dense already does that, big dawg.
Read the ISSCC slideware.
Sure, whatever it takes to serve >80% of the typical user's needs.Doesn't even need to go that high, most industry LITTLEs are 1.8ish.
You'll laugh but I think if Strix Halo ends up being popular with OEMs, it'll be because of AI.
AMD's also doing some real funky SRAM stuff for dense.But the combined effect of reducing buffer cells due to a lower clock target + prolific use of a high density library should result in a very compact, power efficient core
The real question is just how castrated Z5LP really is.but it will be interesting to see how much small AMD got it down to.
yeah needa ask what's the standard (for Apple) LITTLE cluster residency.Sure, whatever it takes to serve >80% of the typical user's needs.
see? very smart.I think that it'll be most popular with CAD users or people dealing with 3D graphics.