adroc_thurston

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• • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    Means the margins are obscene because the volume is tiny. No it means the volume is tiny. You can't just scale hybrid bonding capacity...

    Yesterday at 6:26 PM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    Those are fake numbers for design costs. Like they're not real, this (wrongly) assumed the vendor does everything in house. Which no one...

    Yesterday at 2:30 PM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    You do understand that DIY CPUs have obscene margins, don't you?

    Yesterday at 1:41 PM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    Kind of? It's inherently a slow process that's also kinda expensive.

    Yesterday at 4:23 AM
  • adroc_thurston replied to the thread Question Intel Mont thread.

    no. You really need to talk to some actual real SIMD people. Well neither will ever have any SIMD code running on them. no it didn't...

    Tuesday at 5:40 PM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    AMD isn't Intel in case you forgot that.

    Tuesday at 12:51 PM
  • adroc_thurston replied to the thread Discussion RDNA4 + CDNA3 Architectures Thread.

    because RDNA4 was not supposed to be cheap. really funny right

    Monday at 5:55 PM
  • adroc_thurston replied to the thread Discussion RDNA4 + CDNA3 Architectures Thread.

    Yeah lol they do it all the time later in the product lifecycle. You won't believe the places you can find AD103 in. Some NV SKUs become...

    Monday at 5:39 AM
  • adroc_thurston replied to the thread Discussion RDNA4 + CDNA3 Architectures Thread.

    Efficiency is not the design point for anything RDNA4. You can just like disable IMC segments you know. Tonga is like the most notable...

    Monday at 5:16 AM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    Uh no brother that's not how that works. It adds 4 cycles and half speed caches are just not happening, that's terribly slow under all...

    Sunday at 11:33 PM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    Because you need to run SRAM macro at Real Actual Speeds.

    Sunday at 5:29 PM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    You're so close man. So damn close.

    Sunday at 2:20 AM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    That's really not what it is man.

    Saturday at 9:57 PM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    You want less NUCA domains, not more. Not enough SoIC wafer starts in the world for that. Not really you just want the least amount of...

    Saturday at 5:02 PM
  • adroc_thurston replied to the thread Question Zen 6 Speculation Thread.

    Well there's more to that thing than meets the eye.

    Saturday at 5:21 AM

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