Yes, but I assume it won’t purely be a tensor processor. The NPU on the current A&M chips exist along with CPU and GPU. Some of that type of processing will be required as well. And I/O.
The AI custom silicon perhaps could also be used on the studio/pro in a multi-chiplet configuration. Depends if there is a unifying architecture behind this effort across the product stack.
Aren’t the Zen 5 EPYCs coming later this year? Since the platform doesn’t change(?) from Zen4 to Zen5, I was hoping next Threadripper is released early to mid next year. I can’t wait even that long anyways. Thanks!
I haven’t been following this thread so I have a quick question for the forum members. I’m looking to acquire an HP Z6 G5 7995WX workstation, but before I do I’m curious when the Zen 5 version (128 cores?) of Threadripper chip is expected. Thanks!
Additionally, the Birch Stream (BS) SP socket supports 8 memory channels, while the AP supports 12. Intel sees the need for two different sockets for market segmentation reasons. BS supports both Granite Rapids (GR) and Sierra Forest (SF).
Each of the GR compute chiplet has 4 memory channels...
As I understand things, a process doesn’t necessarily dictate how SRAM or any other circuit is designed. So Apple can use it with TSMC, or any another fab, exclusively in their own SRAM designs. But note that the patent seems to be FinFET only, so it would not apply to N2, where BSPDN is first...
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