Recent content by ashFTW

  1. Discussion Apple Silicon SoC thread

    Separate CPU and GPU designs, interesting!
  2. Discussion Apple Silicon SoC thread

    Thanks! Yeah I figured it out from the comments on the original video. Should have reported it back here ..
  3. Discussion Apple Silicon SoC thread

    Anyone know what he is using as a rack system? I may want to get something like that as well for the lab. Thanks!
  4. Discussion Apple Silicon SoC thread

    Yes, but I assume it won’t purely be a tensor processor. The NPU on the current A&M chips exist along with CPU and GPU. Some of that type of processing will be required as well. And I/O.
  5. Discussion Apple Silicon SoC thread

    The AI custom silicon perhaps could also be used on the studio/pro in a multi-chiplet configuration. Depends if there is a unifying architecture behind this effort across the product stack.
  6. Discussion Apple Silicon SoC thread

    Finflex seems to be already in use
  7. Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Aren’t the Zen 5 EPYCs coming later this year? Since the platform doesn’t change(?) from Zen4 to Zen5, I was hoping next Threadripper is released early to mid next year. I can’t wait even that long anyways. Thanks!
  8. Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    I haven’t been following this thread so I have a quick question for the forum members. I’m looking to acquire an HP Z6 G5 7995WX workstation, but before I do I’m curious when the Zen 5 version (128 cores?) of Threadripper chip is expected. Thanks!
  9. Discussion Apple Silicon SoC thread

    6 graphics cores, not 6G wireless.
  10. Discussion Intel current and future Lakes & Rapids thread

    Additionally, the Birch Stream (BS) SP socket supports 8 memory channels, while the AP supports 12. Intel sees the need for two different sockets for market segmentation reasons. BS supports both Granite Rapids (GR) and Sierra Forest (SF). Each of the GR compute chiplet has 4 memory channels...
  11. Discussion Intel current and future Lakes & Rapids thread

    Intel E-core Xeon line: Sierra Forest 2024 (Intel 3) -> Clearwater Forest 2025 (Intel 18A) -> Cooper Forest 2027? (Intel 14A?)
  12. Discussion Intel current and future Lakes & Rapids thread

    Most likely that’s 80 cores, single socket. The AP version should be 120.
  13. Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

    As I understand things, a process doesn’t necessarily dictate how SRAM or any other circuit is designed. So Apple can use it with TSMC, or any another fab, exclusively in their own SRAM designs. But note that the patent seems to be FinFET only, so it would not apply to N2, where BSPDN is first...
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