FWIW, here is my take. IBM corporate management said in no uncertain terms to get the merger deal done. IBM technical management said they had to maintain among other things access to the 14nm eDRAM process. They spent big bucks JOINTLY developing it as well as needing it for mainframe and...
I thought some here estimated about 270mm^2 for all the I/O stuff on the hub chip. If so, then 256MB of 14nm eDRAM L4 will be about 150mm^2 and WILL fit. My question is would AMD design it in a thick box partially depleted SOI process? They used to use such a process at 28nm. So they surely are...
nextplatform.com
very interesting article about buffered memory for Power 9 (Centaur tech)
...snip "We really want to attach our memory with a SERDES design, with differential signaling. So we really want to get to a SERDES solution to talk to the outside world" It's not clear how much of...
the 12nm process was almost entirely a PROCESS upgrade that did not require any substantial re-design. If I remember, the main change (among others) was an optimized fin etch profile and a 4nm reduction in DIBL allowing shorter minimum channel length.
I just realized the 14nm Global process with embedded DRAM as used for IBM Power 9 is on thick SOI. The process would look different on bulk and is more complex. I doubt very much AMD would design their hub chip in partially depleted SOI with thick BOX. So I'd have to say the eDRAM is not...
That sounds good. And perhaps a different I/O chip for high end gaming by replacing the iGPU with L4 cache and using a 8 core chiplet. All 14nm I/0 chip designs would be pretty cheap these days at GF. I suspect.
it's 16MB L4 buffer on EACH of (8) Centaur chips (one for each memory channel) or 128MB if they did it on one hub chip.
https://www.anandtech.com/show/9567/the-power-8-review-challenging-the-intel-xeon-/7
this was on Power 8 and done in 22nm SOI. Power 9 was done in 14nm FinFET. I suspect...
perhaps eDRAM similar to Centaur technology on Power 9. It could be 256MB or possibly even 512MB on the 14nm process with eDRAM used for the memory hub chip on Power 9. Global owns the process since the IBM Micro/GF merger. Your thoughts?
https://en.wikichip.org/wiki/ibm/centaur
baby, you just ain't seen nothing yet!
https://www.youtube.com/watch?v=7miRCLeFSJo
AMD at Computex. Lisa was just glowing about 7nm EPYC 2 results in the lab. She claims sampling to customers very soon. It looks like an April 2019 launch could be a lock. Having known Lisa well, that is about...
LOOK AT THIS. This is the NEW EPYC based 2RU Cisco box. It contains (4) 2 socket nodes or 4x64cores/node = 256 cores.
The corresponding Intel 2RU configuration contains (2) 2 socket nodes or 2X56cores/node =112 cores.
The corresponding Intel 4RU configuration contains (4) 2 socket nodes or...
youtube.com
AMD's "Starship". It's also known as Rome.
It's 48C / 96T on 7nm technology. It's coming to venders near you in early 2019.
Nothing's Gonna Stop Us Now.
https://www.semiwiki.com/forum/content/7496-imec-technology-forum-gary-patton-globalfoundries.html
It sounds like Agnello and the IBM folk did OK. I worked for Patton for a while in the 90s. He is pretty good also. Based on this, it looks like GF is on schedule to begin (as fast follower...
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