Apart from this not really being disputed just because of German(-ish) being spoken in some valleys around there, there is another Verano next to Piacenza 😉
https://maps.app.goo.gl/NpXM9gDRvrdDgNrKA
Then you are pretty much alone with your line of thinking. Every piece of information and every half credible leak points to 32c for Venice Dense and 12c for Venice and Desktop.
To keep per core RAM BW constant, they would need a 128 GByte/s D2D interface BW compared to 64 GByte/s GMI narrow. To keep RAM BW : CCD BW of roughly 10:1 constant, they would need around 170 GByte/s.
That should obviously be the range for Desktop Venice too, finally allowing it to use all the...
@adroc_thurston is on record for stating that they have a separate CCD.
I still find this a bit unbelievable for such a small volume part, but we will see.
That'd be a surprise for me - and not in a good way. Somewhere I can hear the benefits of scale scream.
As you seem to have much more insight than me, I am inclined to believe you for the time being - as stated before, I am just speculating.
But I really expected them to put to good use of what...
I am saying that, as was the case with Zen4 as well, Zen5 has two GMI links for EPYC and standard-Ryzen (only one used) SKUs and additionally has another way of interconnect for Halo. The latter one should be rather small and in some yet unidentified area.
Just as with MI300A, I am expecting AMD to use fully separate function blocks on the CCD for the interconnect on Halo.
History repeating itself: Zen3 already had TSVs for 3D$ that we only found out about later on.
Zen4 already had the SoIC blocks for MI300A that we only found out about later...
As they will completely change the underlying technology, almost nothing is known. From a pJ/bit POV we are talking about <2 pJ/bit vs. 0.15 pJ/bit. So even quadrupling bandwidth to 256 GB/s per CCD will still bring peak energy savings of more than 50% for the interconnect. Also die area saving...
For Zen4 there was nothing to do, because it was the same CPU family 19h.
For Arrow Lake as well as for Meteor Lake there are changes needed, as the OpenHWM library uses an Enum to identify Intel CPUs accordingly.
Might do that in the next couple of days as well.
Hi @mmaenpaa
So, adding support for Zen5 was not as trivial as I had hoped for - but I nevertheless hopefully was successful.
Could you please do me a favour and test the modified OpenHardwareMonitor release I just created...
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