Then you also should see
they try this kind of new paradigm since X360
but PC not catching up with the paradigm
good article back then from
http://arstechnica.com/features/2005/05/xbox360-1/
so MS need to pushed the entire ecosystem into streaming model
which is funnily is actually why X360...
you should see Mike Mantor paper
there is no coincidence he recently awarded by AMD
http://www.hpcwire.com/off-the-wire/amd-promotes-renowned-graphics-architect-michael-mantor-to-corporate-fellow/
http://ir.amd.com/phoenix.zhtml?c=74093&p=RssLanding&cat=news&id=2118863
he is a father of X360...
X1 using DX 11.x not even latest XDK
too bad games still not use it ...
MS seems must pleased IHV too + some politics
The actual X1 performance DX11.x versus PC DX11, this is from single thread
==================================
And Max Deferred context under DX11 core is way beyond PC or...
you reading wrong Jeff
always downplay abit on X1 news
but add more sauce to the PS4
when there is nill fact of tensilica on PS4 for example
they not abandoned OBAN
OBAN is eSRAM 3D IC
How they can support BC
they have HPAPU-->
If you have 2 SOC the story told in media wil be
1st they said...
this is just only several work resume that hinted ....
the test chip is 3D start with 32nm, the final one is 22nm (fabbed at CPA)
the Jag SOC is 28nm TSMC (later on)
that arm block is for PSP
not related to MCU or DSP, or Tensilica
not all is tensilica based
some FPGA etc
you see the eSRAM has lighter color vs the surrounded
because it is stacked
the reason chipwork not doing cross sectional cut
when they do to pS4
same thing to techinsight doing cross...
From Hotchip
John sell said eSRAM can be accessed from CPU
that from Programmer POV
eSRAM is basically addresable
this is the fast embedded SRAM one the one that has CPU access
==================================================
real immutable in operation one !!
esram = ehanced SRAM with...
because the eSRAM is 3DIC
highspeed eSRAM is immutable
targetted for streaming DX12 concept
front end doing the hard work
then stream
the addresable "eSRAM" is slower one
it is why in XDK they describe 2 things
addresabel eSRAM act like giant scratch ram forced programmer to use...
you have to check the other page
in XDK they said 4 GDS, thats why there is GDS to GDS trf function
so it is fit
plus on XDK they said the extremely high BW esram no CPU connection
but cache like eSRAM has CPU access you can bet where this thing goes
it is funny that Charlie the one that hated...
BTW to Jeff and other this is updated paper from John sell
please dont use Hotchip one
as it is not even tell the true story of X1
this is the preprint version
of John sell with 2nd texture cache goes to CUs
means there is 4 block
also remember texture cache only goes to CUs
the 768 operation...
as days goes By
people forget what PIM is
1st commercialized PIM is eDRAM in X360 that in 2D design
(from outside it is just 20-32GB/sec) from inside is natively Huge BW
X360 has 192 ALU inside the emb RAM = PIM
with big money and multi billion in RD
you can guess the next evolution of eDRAM...
Just for fun this is Mike Ignatowski patent from IBM then Microsoft --> MULTI ISA (PPC/X86 etc)
then this is when AMD CTO congratulate Mike for success of AMD PIM (Fast Forward prj)...
@Jeff of course PIM has to be low it is clocked same as eSRAM clocked
you know why Charlie hinted low clock 426Mhz for long
i know charlie dont like MS so do most people at S|A (i dont know why)
but his hint are correct
first PIM is designed to be multi stacked
the CPU has to be under SRAM or...
Oh BTW AMD Fast forward (processing in memory) PIM architect has Patent for Microsoft for multi ISA
one of PIM Architect is Mike Ignatowski
PIM also clocked low (like my speculative of esram Speed)
PIM also sized in same size as current HBM which is also same as eSRAM
which is 35-40mm2
also...
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