Recent content by BumJCRules

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    DRAM latency...

    Okay... Now you've done it. I had 16Bit before and I thought you corrected me. So what you are saying is that I was correct before with quad-word being 64B. (Bytes or 512 bits) Ugghhhh!!!! I understand the physical structures. I just need to understand how the delays, protocols, etc. So...
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    Mass of Light?

    I agree... That is a good way of thinking about it.
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    DRAM latency...

    I don't know where to go from here.....? I was incorrect with my look at the P4X266 chipset on the Trinity 510 S2266 motherboard. That is a P4 board and had a 3.2GB/s FSB, 4 channel by 100 MHz by 64bit. So the percentage is not correct. The numbers will also be skewed because of the prefetch...
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    DRAM latency...

    "Wait a second I don't understand one thing. Isn't more like tCAC/tCLK >=CL" See here. "I didn't think the tCAC was variable. It is set by the design of the DRAM. Where did you get that tCAC was only 10.5 ns? 1.4 X 7.5 = 10.5ns" The rating for 400/3MHz signal, or 133.33MHz, is 7.5ns...
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    DRAM latency...

    "Bum, you're completely off on your calculations." How so? You said... "From fastest to slowest flavor on a given clockspeed (in terms of CL, tRC, tRRD, tRP, tRAS) you typically lose four to five clocks - not in a second, but on every block of eight quadwords (a "burst"), and on every single...
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    Trouble understanding Time Dilation

    I do not see where the "Earths Coriolis effect" fits into this. Do you mean an observer from space looking at the earth? How does air that is pushed by the friction with the surface of the Earth work with "percieved" changes in sight or sound? (Both using electromagnetic waves.)
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    Mass of Light?

    How would speed add mass? It wouldn't. E=MC^2 Speed is some form of constant. Light travels at slightly different speeds through various mediums. There have been experiments where photons have exceeded the speed of light. The Photons were accelerated through the test chamber and exited...
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    Math Question

    It is sarcasim... Sorry. I thought that I could use some after that comment about exact figures. Like saying 400/3MHz. People don't understand it. So most people say 133MHz, even thought it is an aproximation. Most people need hard figures to make it compute in their minds. May most of you...
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    Tecnically can DDR-II compete with Rambus ?

    cheeta05r, Nice to see you on another board. I still am looking for a home. Tom's has been boring lately and I get sick at looking at a dark screen at GenMay and Hard Forums. Anyway... I agree. Static memory would gratly improve memory systems. I would like to see them impliment large...
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    Hammer effective bandwidth for the memory?

    "How does memory access work in a hammer multiprocessor setup? If one processor1 tries to access memory that's physically connected to processor2, does processor1 have to communicate with processor2 and tell processor2 to fetch the memory and then processor2 communicates the data back to...
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    Math Question

    heliomphalodon, You said... "Close, and probably the right approach, but once you introduce an approximation you have lost rigor. A correct proof must be exact (or symbolic). I think your use of the Law of Sines is probably the key to a clean result, but we're not there yet..." Please give me...
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    Math Question

    Since ABCD is a Square, Postulate #1 - Side A, B, C, D all equal 10 units in length. This is just a number that I am using. Postulate #2 - Singe all the angle in a square are 90 degree angles, all of the side are equal lengths. With that being said... Use the law of sines to figure out...
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    DRAM latency...

    Good point. One reason that RDRAM has such high latencies. A lot of banks and a lot of reactivations of those banks not to mention that the biggest delay for RDRAM is the fact that the sense amps are shared with adjacent banks. However having tons of them helps improve that latency problem...
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    Hammer effective bandwidth for the memory?

    "Cores communicate with eachother through 16bit coherent HT links." However in a dual+ system there are two HT links in each processor core. If you had two cores, there are two on each and thus they can talk to each other using both. If you use more that two processors in the setup they still...
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    DRAM latency...

    "1. Clock speed 2. CAS latency 3. tRC 4. tRAS 5. tRP and tRRC" I agree whole heartedly on the speed for #1. CAS and all of the others are no big deal. No offense but from the most aggressive to the least aggressive setting that is only 18 clock cycles of delay/latency. At current DDR333...
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