Why would I be mad?
Chips are hard... I get that... Look at the Raptor Lake issues, that ended up being an issue with the clock tree which is incredibly complex and I could see any company running into that issue...
I think that Intel made decisions with Arrow Lake that didn't quite pan out as...
That I take full responsibility for. I miscommunicated what I wanted to have happen to the rest of CnC and by the time I realized the miscommunication the site had already been moved over to Substack.
My original plan was to have the Substack up but that be the secondary site with something...
I think what is going on is that Vera will support CXL on its PCIe lanes and you will be able to attach DDR5 modules to Vera via CXL.mem.
Which makes sense for Vera considering that it is just a memory expander for Rubin.
1) I highly doubt it's 50W for just the CPU cores unless they were not very performant cores (And as we all know, Jensen would never lie... Right guys... Right?!?!)
2) Vera isn't LPDDR6, it's LPDDR5X... likely LPDDR5X-9600 on a 512b bus...
Tell me you haven't heard of AMD K12 without telling me you haven't heard of AMD K12...
That was AMD's first custom ARM core and it went nowhere...
And no, AMD won't abandon x86... that is a silly train of thought... there is far too much money in the x86 market that will never go away...
Irony being that by Zen 7, or whatever it is called, launches, AMD could have added the APX extension to the core which would make the move to ARM make even less sense IMO....
Heck, they could also have moved to x86S which removes alot of the legacy stuff that folks like to complain about....
So...
Like I said, I think you are reading too much into it.....
At this point we don't know enough about what Lion Cove (or Skymont for that matter) actually looks like to assume if the image actually is showing anything notable.... sure there are folks like Raichu on Twitter that claim certain...
Yeah..... Getting the NPU to work was a pain and in the end it ended up just being faster to run stuff on the iGPU....
Maybe with LNL, STX, and SDXE that will change and we will have to test it when those CPUs are available, but for right now we just didn't see the point of the NPUs in MTL or in...
Except that's not how Intel sets up their math scheduler...
Here is what Golden Cove's Math Scheduler looks like.....
Notice how the FP ALUs are on the same ports as the Integer ALUs..... That's what I expect of Lion Cove.....
I think you are reading way too much into this diagram.....
8 way Dispatch and Rename seems reasonable as does the 6 AGUs and 2 Store Data ports likely split evenly between a separate 4 port load schedule and a 4 port store scheduler like Golden Cove.
But the assumption that you are going to...
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