Wonder what the extra cache SKU is and when it comes out? stacked? Or all in one die (hopefully P Core only, imagine either 16P Coyote/Griffin Cove Cores w/ 144+ MB of Cache in a single die, would be sick).
Hopefully they do it P Core Only, imagine 12 or more Griffin Cove Cores with RZL-S with all that extra cache and crazy fast DDR5 with low latency? Insane gaming performance.
If that 144MB L3 compute die exists wonder what the core count would be? If Intel is releasing BTL-S to Consumer (this seems to be the case: https://videocardz.com/newz/intel-preparing-budget-core-5-120f-6-core-cpu-featuring-only-p-cores) I wonder if they make NVL & RZL extra huge cache versions...
Wonder if there's a Zen 6+ in the works? I mean I can see N2P Zen 6>A16 Zen 6+ >A14 Zen 7 on AM6?
I mean AM5 effectively had 4 gens for Consumers with Zen+, wouldn't suprise me to see A16 being used for a Zen 6+ to recreate a sense of longevity for AM4 had for AM5 and to compete against RZL...
I know, which is why an A16 CCD for Zen 7 may come out as early as Q4 2027 to compete against it on Desktop (and also to trial funky stuff like the Zen 7 3D core).
Probably but Zen 7 sounds ambitious in a lot of stuff, so do it on AM5 first with sacrificing a bit of performance ala Zen 3 and then Zen 8 can be akin to Zen 4 (with maybe an increase of core count to 16 per CCD). And also to compete against Razor Lake-S.
Yeah that makes sense, I think late 2027/early 2028 sounds more akin A16 for Consumer CCDs with A14 being for Zen 7 Dense later on when it comes to mass production and stick to AM5, and then 2029 sees Zen 8 with AM6 & CCDs using A14 SPR (TSMC BSPD).
Probably, big wonder if Intel is all in on Druid being the big return by being MCM based (wonder if they can get glass substrates for that in time).
With Battlemage, Intel still needs to work on PPA on architecture. Maybe N4 won't be so bad if they can massively improve it to the extent it's...
Wonder if we'll see seperate P Core and E Core chiplets with future architectures, would be nice to see P Core chiplet with stacked (Adamantine L4) Cache for example.
There isn't a sign of Quadro Blackwells in the next few months, suspect they are waiting for 3GB Modules sometime in 2025 to whack them on and have them use 96GB of VRAM on both sides of the PCB.
Considering how this lineup as rumoured I think Nvidia planning a Super refresh for the 5070 & 5080 with 3GB Modules (so 18 & 24GB VRAM respectively) and higher clock speeds against RDNA 5. Hell maybe a 5090 Super with more SMs enabled (say to 180-182) and clocks go up a bit with 48GB VRAM. Like...
Hmmmm, doubling of Raster Engines and ROPs per GPC (may be 4X the ROPs?). Wonder what Jensen cooking with Blackwell because it seems the SMs are really going to be quite different to Ampere & Lovelace?
On die size I do wonder if they'll do not 128 MB L2 Cache but 64 which makes way more sense...
Plans probably changed.
I seriously doubt MTL & ARL will be on the 'same' 'gen' considering some rumours have a big ST increase between the two architectures. I think Intel has ARL-S on TSMC N3 for the CPU tile so they can release it sooner than later.
But if ARL-S is on TSMC N3 being able to...
I really cannot see Intel having RPL-R take on Zen 5 & Zen 5 V-Cache if that's true (though DigiTimes AFAIK have been inaccurate at times with MTL partially having TSMC N3), because if they can't get MTL-S out then they have to get ARL-S out ASAP even if it's just a less ambitious core count...
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