Recent content by evilr00t

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What controls Turbo Core in Xeons?

If you have one of the cpuid=0x306f2 QFxx C0-step CPUs, congratulations, your chip runs faster than the official ones, although I wouldn't run PCIe gen3 on them! If, on the other hand, you have a cpuid=0x306f1 B-step CPU, you'll probably not be able to apply this hack as the chips usually need...
- evilr00t
- Post #2,128
- Jan 2, 2018
- Forum: CPUs and Overclocking
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What controls Turbo Core in Xeons?

if you're using an ES1 chip that uses microcodes with a mask of 0x80000000, you almost certainly won't find it in the cpumcupdate dll unless you add it yourself. That should be able to be extracted from your BIOS if it has a 0x80000000 mc update, which it almost certainly does.
- evilr00t
- Post #1,915
- Nov 23, 2017
- Forum: CPUs and Overclocking
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Working SD card RESISTING 10+ ways of FORMAT

Your SD card is toast, and becoming read-only/write-resistant is the Right Way for a solid state drive to fail. RMA it if there isn't anything valuable/sensitive on it, hammer it otherwise.
- evilr00t
- Post #8
- Nov 17, 2017
- Forum: Memory and Storage
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What controls Turbo Core in Xeons?

I have no doubt the hack works on earlier chips, however, there are many caveats to working with early engineering samples. ES0 (306f0) chips are garbage, turn them into keychains. I've never managed to get one to boot into Windows. I wouldn't expect any shipping BIOS to keep microcodes for this...
- evilr00t
- Post #1,730
- Oct 19, 2017
- Forum: CPUs and Overclocking
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Dual XEON 2696 v4 + Supermicro X10DAX Build - BSOD frequently - please help

9812 - nvidia driver bug The rest: whea uncorrectable. 0xf200020000010005 - Proc 67, bank 0 - 14265 0xb200000000010005 - Proc 66, bank 0 - 14250 0xf2001b8000010005 - Proc 66, bank 0 - 14078 0xf200d88000010005 - Proc 66, bank 0 - 10765 Bank 0 is the CPU L1 instruction cache. Notice how all of...
- evilr00t
- Post #7
- Oct 14, 2017
- Forum: CPUs and Overclocking
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Dual XEON 2696 v4 + Supermicro X10DAX Build - BSOD frequently - please help

The last xeons to need mismatched stepping support were the Sandy Bridge Xeons, so if your cpuid's don't match, you're running an ES with a retail stepping of the chip. That's unsupported and will blow up. whea uncorrectable error bad hardware - post your crash dump (you should have a minidump...
- evilr00t
- Post #5
- Oct 13, 2017
- Forum: CPUs and Overclocking
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CPU for Floats crunching

That's interesting as hell. Is Bristol Ridge the first consumer GCN implementation to do 1 : 2 SP : DP?
- evilr00t
- Post #28
- Sep 16, 2017
- Forum: CPUs and Overclocking
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CPU for Floats crunching

I'd love to see these reports myself. IIRC GCN3 (Tonga/Fiji) had 1:16 SP:FP ratio. The A12's IGP has about 1.1 SP TFLOPS, I'd be surprised to see 500 DP GFLOPS out of it.
- evilr00t
- Post #24
- Sep 16, 2017
- Forum: CPUs and Overclocking
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Vega refresh - Expected? How might it look?

There seems to be a lot of FUD around nVidia's equivalent to AMD's HBCC (iommu, copy engine, virtual addressing, paging). The IOMMU and copy engine have been around since before Kepler (unified memory). *see edit below What's new in Pascal is "49-bit virtual addressing and on-demand page...
- evilr00t
- Post #139
- Aug 31, 2017
- Forum: Graphics Cards
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AMD Radeon RX Vega 64 and 56 Reviews [*UPDATED* Aug 28]

I have a hard time believing this. A simple OpenCL program to allocate 6GB of device memory (and read through it sequentially periodically, to see the impact of HBCC page migration) should have the same impact as restricting VRAM to 2GB.
- evilr00t
- Post #1,272
- Aug 28, 2017
- Forum: Graphics Cards
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Vega refresh - Expected? How might it look?

This seems to be a Pascal (CC6.0+) feature, and doesn't seem restricted to GP100. Citation needed on paging granularity, and why this matters. Here's a dump of a modified deviceQuery on my GP107 card: Device 2: "GeForce GTX 1050 Ti" CUDA Driver Version / Runtime Version 8.0 / 8.0...
- evilr00t
- Post #95
- Aug 27, 2017
- Forum: Graphics Cards
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What controls Turbo Core in Xeons?

I think the QS0/C0 chips have higher turbo multipliers.
- evilr00t
- Post #1,413
- Aug 27, 2017
- Forum: CPUs and Overclocking
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What controls Turbo Core in Xeons?

Dual CPU boards usually route PCIe lanes out from each cpu, so depending on the number of Wellsburg chips, could be 40 (CPU Integrated IO) + 8 (Wellsburg PCH) per CPU. Typically you only see one Wellsburg [edit: per board, not per CPU] though - multi-PCH setups are very unusual even in the...
- evilr00t
- Post #1,324
- Aug 13, 2017
- Forum: CPUs and Overclocking
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Good SATA port add-in card?

I would be _really_ careful with any Marvell SATA controller with drives over 2.2TB (3TB+). I've encountered silent data corruption, where occasionally, if writing to an address above 2TB, it'll subtract 2TB and write to that address instead; I'm glad I had btrfs to tell me that corruption had...
- evilr00t
- Post #3
- Aug 9, 2017
- Forum: Memory and Storage
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What controls Turbo Core in Xeons?

If I'm interpreting this correctly, the bootstrap processor is usually CPU0, so I'd put the newer (retail) chip there. It probably doesn't matter because both are QS-C1 chips (the retail version just has the ES flag unset).
- evilr00t
- Post #1,292
- Aug 8, 2017
- Forum: CPUs and Overclocking

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