You'd probably be better off putting him (and some others) on mute. Best not to feed the trolls. But regarding Discord, I don't think you'd like the forum equivalents there much. Way too fast paced and meme heavy. Gives me a headache.
I don't think there is anything amazing about them? If...
I'm not aware of any way to tell if they don't include it in either the brandstring or the label, nor do I know why it's a thing. Never seen an example myself to learn why.
Just for the record, don't rely on the brand string for an accurate metal stepping number. You'll sometimes see "silent" steppings that the company doesn't want visible at a product level. And there will probably be more shenanigans with chiplets in the mix.
AMD may not always ship their lead Zen product on A-step silicon, but they've done it for the follow-ons like their mobile chips. That's a tradeoff they make. By serializing the APUs behind the desktop IP implementations (CPU and graphics), they're able to minimize the risk of bugs an...
It takes about a quarter no matter what (for a modern leading edge process). I'm only familiar with TSMC's timeline, but it's clearly asymptotic around 4-5 months, no matter how many millions extra you're willing to pay. Even if Intel was able to shave off a week for their internal teams, the...
They always have something that starts with A, but seem to name the derivatives differently. Like the TGL 8c started at P or something. Likewise for the ADL 6+0 die.
And you definitely can't pull off a full layer stepping in a couple of weeks. Even if you taped out instantly (which is...
That's a stupid dual CPU package that no one ever used, except maybe one or two examples in HPC. Was just a way for Intel to advertise higher density. And, Cooper Lake is just another Skylake refresh, though I guess technically they added more UPI lanes.
They can't blame the node for everything. Tiger Lake took two steppings. Alder Lake took three. That's entirely on the design side, as would be most of SPR's trouble. And as we saw particularly with the latter, it creates huge delays. Imagine how different Intel's competitive position would be...
They're both embarrassing for Intel. SPR is just so bad that it single-handedly shifts the Overton window. At basically any other company, RPL would be an A-step PRQ, and SPR B-step, C at worst.
And that "experimentation" costs how many millions of dollars and months of development per tapeout...
There were rumors about an "Alchemist+" dGPU at some point. Maybe the IP will still exist in ARL. I am curious about the reason, though. Would presume it be schedule related, but ARL doesn't seem like it's coming particularly early either.
The drop in GPU competitiveness in the P/H segment will...
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