Recent content by gai

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Discussion General CPU µArch Research Thread

The 2023 paper (Clockhands) is an iterative improvement on the 2018 paper (STRAIGHT). In both cases, the ISA is modified to replace architectural register identifiers with distance-based identifiers. This means that the source operand directly refers to a source instruction, rather than relying...
- gai
- Post #12
- Mar 6, 2025
- Forum: CPUs and Overclocking
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Discussion General CPU µArch Research Thread

The baseline design is somehow spending a rather large 45% of its total dynamic energy on the issue queue in the first place. One is required to infer why claimed energy savings are even more than this, because the authors do not provide any energy figures other than for the issue queue. You...
- gai
- Post #4
- Feb 9, 2025
- Forum: CPUs and Overclocking
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Question CPU Microarchitecture Thread

I previously had searched for only the cache sizes in IBM z17 (reportedly 32K L1I and 32K L1D), but I didn't look at it closely enough: the snippets from Hot Chips are for the DPU, a separate part of the system architecture from the main CPU cores. I apologize for the error. Indeed, IBM zSeries...
- gai
- Post #68
- Nov 14, 2024
- Forum: CPUs and Overclocking
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Question CPU Microarchitecture Thread

The explanations above appear sound to me. Duplicating information in a CPU to reduce timing criticality very frequently worth the area cost. However, none of these techniques provide any explanation about the originating question on page 1: why is Qualcomm's 96 KiB, 6-way L1D cache so much...
- gai
- Post #66
- Nov 13, 2024
- Forum: CPUs and Overclocking
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Question CPU Microarchitecture Thread

Yes, after excluding the hardware and design choices that solve the aliasing problem in any particular processor, there's no additional hardware requirement. This is a tautology. The cache systems that you are describing maintain physical indices to guarantee that synonyms cannot allocate to...
- gai
- Post #63
- Nov 12, 2024
- Forum: CPUs and Overclocking
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Question CPU Microarchitecture Thread

Yes, you have briefly described how IBM has designed additional hardware to prevent physical aliasing across different sets in the first-level data cache. This additional hardware is not free and would not be required in a physically-indexed cache. Virtually-indexed caches must provide alias...
- gai
- Post #51
- Nov 11, 2024
- Forum: CPUs and Overclocking
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Question CPU Microarchitecture Thread

There's no difference between VIPT and PIPT when the cache is small enough, and this is where the implementation becomes much nicer. Hence, the 48 KiB Zen 5 L1D$ and the 48 KiB Lion Cove "L0" D$, which use 4K page sizes, are both 12-way PIPT. When the first-level cache uses VIVT, it requires...
- gai
- Post #25
- Nov 11, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

Each company will produce the fastest design that they can make within their area and power budgets. Neither clock frequency nor work-per-clock alone can predict the final performance, so they are only intermediate indicators. Here is a basic formula that is taught in any computer architecture...
- gai
- Post #8,038
- Aug 14, 2024
- Forum: CPUs and Overclocking
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Discussion Google Tensor SoC thread

The title says 多核, which is multicore. You would see 単核 for single core (i.e. single thread).
- gai
- Post #49
- Aug 9, 2024
- Forum: CPUs and Overclocking
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Question Apple M1 vs AMD Ryzen 5000

Both M1 and Ryzen 5xxx are very fast. Unfortunately, the performance of a CPU cannot be reduced to a single number. In cases like this, where the two processors are close in speed, the answer will vary from program to program. We have some comparisons available, such as the following article...
- gai
- Post #2
- Dec 7, 2020
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

Although I cannot speak for Maynard regarding his comments on way prediction, I would like to clarify that "flush" should not be considered a synonym for non-selective replay. I neglected non-selective replay in my earlier reply, but it is a third option. In short, imagine a selective replay...
- gai
- Post #636
- Nov 17, 2020
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

Both flushes and replays are techniques to recover from incorrect speculative execution state. However, their cost, both in energy and in performance, differs wildly. In this context*, a flush refers to completely removing all traces of program execution past a certain point in architectural...
- gai
- Post #619
- Nov 17, 2020
- Forum: CPUs and Overclocking

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