People who have followed everything on Digital Foundry, use a magnifying glass, and have superhuman fast visual neurons with a trigger rate that can keep up with the FPS, will really appreciate the RTX 5090 above the RX 9070 XT.
Diminishing returns for the rest...
Actual die shot of the RX 9070 XT together with the AMD Ryzen CPU.
The RX 7900 XTX die sizes stem from AMD itself:
https://ir.amd.com/news-events/press-releases/detail/1099/amd-unveils-worlds-most-advanced-gaming-graphics-cards
https://videocardz.com/newz/amd-navi-48-rdna4-gpu-for-radeon-rx-9070-pictured-may-exceed-nvidia-ad103-size
I did a perspective correction but the ~390 mm2 holds.
The ~390 mm2 is reasonable accurate. The above is an equal scale comparison.
Similar die-size, process, memory size, memory bandwidth, raster and RT performance as the RTX 4080.
NVIDIA has apparently stopped selling the RTX 4080 altogether ...
The 24 bit channels, with two 12 bit sub channels do allow both PAM3 and NRZ versions in an efficient manner.
For NRZ only you would simply use bus sizes with powers of 2.
I don't know if they have given up on PAM3 versions already?
PAM3 for LPDDR6 presumably
=========================
2...
Indeed,
A single mobile LPDDR6 CAMM2 memory module will max out at ~500 MB/s. That's double the Strix HALO bandwidth or halve the RTX 4090 bandwidth.
Expect beefy iGPU's in the not so far away future.
Trinary signaling can transfer 8x32 bit in 7 cycles over a 24 bit bus. At 14.4 GT/s that...
I don't know, but I do not think so...
Userbenchmark is made and maintained by just a single 46 year old deaf free-lance web designer. He's looking for work to support his familie.
The Zen 5 CCD die isn't thinned anymore like Zen 3/4 to accommodate the X3D V-cache.
Thus: There are no TSV's going through the entire Zen 5 CCD, and they would only end up at the thermal paste / heath-sink anyway.
If these structures seen on the Zen 5 CCD have anything to do with TSV's...
Now wondering if they could possibly have a united 3D V-Cache under both CCD's for the 9950X3D and 9900X3D, with direct L3 connect and bypassing the serial interconnect via the IOD die....
That would resolve a perceived weakness of the current design.
And it would also be an explanation why...
The only change which seems possible is that they have flipped the 3D V-cache die so that the TSV's of the CCD now connect directly to the top metal layer of the 3D V-cache.
In this case the 3D V-cache die itself would no longer need TSV's with the result that the total TSV length is halved...
Using the images of Frizchens Fritz:
This shows the signal / power interconnects on the AM5 Zen 5 substrate and the ball grid array of the Zen 5 CCD that goes on it.
I do not know how you would put the 3D V-Cache die between those two ???
Maybe AMD engineers can do wonders?
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