Fine now these benchmarks look pretty reasonable. They match exactly what was expected from the design issues I mentioned in other threads here. And they have the same issue with not exceeding 2.8 GHz which was the reason for the delay.
They have one or more speed pathes to be fixed in order...
Let me try to explain this fundamental misunderstanding of absolute IPC.
e.g. if you have an IPC of the absolute value x.y that means actually nothing if not used as relative comparison with exactly the same code.
E.g. I have a program that makes in the main loop 20 adds, 5 muls and 1 div...
As we have now lot's of official information from AMD I do not think we can find a lot in such articles. As you say it is likly more speculation because otherwise on which sources they rely on? I did not read the article BTW.
Again stuff from the Aprils fool 2010. It has been identified as fake since 2010 and it is not funny to repost this Bullshit again and again.
It's proven as fake.
Llano is much more powerful than Sandy Bridge. Intel has simply no offering to be able to compete with Llano at the moment. And we all know that Intel is since a long time lacking extremly in graphics market.
On the other side AMD had even less chances than Intel to break into this market. But...
Some comments on this:
First AMD has TWO Fabs in Dresden not one (by Global Foundries). And they are building another one in New York (by Global Foundries). In addition they use e.g. TMSC.
AMD is now again profitable, they recovered from the heavy losses they had by buying ATI.
Next the...
I think you have little knowledge.
Think again what an incredible success Intel had regarding by just adding Port 5 and how little it costed.
I also named the die sizes of chips where it is done like that and how small they are. And Bulldozer where it was done vice versa and how bad the...
You make the mistake to forget to substract the die size consumption of included graphics unit.
Oh what difference ...
Yes a 4C Bulldozer which competes with Dual Core Sandy Bridge regarding performance. I take two similar (as far as you can do that) performing chips and comparing the die...
I do see the die size utilization as a performance issue. As you know you cannot make a chip as large as you want. There are many limits, speed pathes, TDP and finally costs.
AMD will not suffer from initial Zambezi die size. But they already suffer when it comes to Interlagos and they will...
I made a little research on that but the problem is they have the same issue with Deneb and did not remove that so I do not think they will change this with Bulldozer, though I already emphazied in earlier posts that AMD has to fix their uncore die consumption issue.
I don't think there will be...
That is out of question and not the problem. The problem arises from the amount of die space AMD Bulldozer needs to surpass the 4 Core Sandy Bridge. That is almost twice the die space (excluding graphics on Intel) and that causes the real problem, not in 2011 but in the upcoming years. So let's...
From my experience with recent CPU releases and benchmark results which leaked before I can tell that in all cases the final retail performance matched the performance of the pre-release/engineering samples. What might not match is the clock frequency but everything else is okay. Yes there might...
Maybe it does not matter, but false dependencies prevent scheduler from pulling instructions ahead. If there is no false dependency it can pull them ahead using shadow registers. The problem is if the BD does not work exactly as you expect but it could do more ops/cycle you might have...
It is not so good to use 32 Bit operations in 64 Bit code since that might cause false dependencies, though you spread the operations widly over registers.
Changed to 64 Bit only, no false dependencies, I also changed the immediate operations to register operations to not run into decoding...
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