So here's the story on IPC from my perspective.
The original design goal was higher IPC. Back before we had taped out the first processors the discussion came up. I am not allowed to say anything in public that hasn't been vetted past engineering. I specifically asked the engineering...
Benchmarks at launch, like I said.
I am pretty sure that when we launch, both sides in the fanboy war will gear up. Everyone will have their own pet benchmark that proves their point. A year after launch the fighting will still be going on. Not because it matters but because some people...
I have never understood why people get so emotional over things.
If the product is right for you, you buy it. Pretty simple.
That rant reminds me of this: http://www.youtube.com/watch?v=kHmvkRoEowc
1. Let's not.
2. Crap, someone took my slide and changed the titles but did not bother to change the numbers at the bottom.
Phenom has 6 cores, each can handle a 128-bit FP execution which is 4x32. that should be 6x4=24. Magny Cours has 12 cores or 12x4=48.
I will retract the 6282...
If they were official AMD numbers they would be on AMD.com
That is my slide. 128-bit FP is today's SSE.
No, that is a server slide (I made it) and that refers to the current 12-core Magny Cours.
Actually, I think that you are a.) overestimating the impact of sharing resources and b.) undersestimating the impact of Turbo CORE.
If you load 4 threads on 2 modules there is a small impact from sharing, probably between 0 and ~10%, depending on the workload. However, there are also...
My thought is that 90% are fake and the other 10% are not representative of actual performance. Trying to draw any conclusions on performance, in light of how many fakes are out there is impossible.
But you keep going back to AVX-256. Are we talking about client or server. I don't expect to see that anywhere on the client side and only rarely on the server side.
You are aware that FP pipelines are really long, right? And that if you mix AVX and SSE, intel needs to clear the pipeline...
If you think that there is somehow a problem in FP-heavy applications, I'd love to understand how that is.
Each module has a dedicated FP scheduler. The intel architecture does FP scheduling from a shared integer/FP scheduler. The integer thread, the hyperthread and the FP execution all...
How much wiggle room?
You'll know when you don't get a chip next time.
I would assume it is not worth the risk.
All of the press guys at AMD for the overclocking event had NDAs that said you cannot say anything until the press release went live.
How many of them posted anything...
We never get to month or week granularity, only quarter. The only time that I have taken it to month granularity is when it is the 3rd month of the quarter and we have promised to launch in that quarter. At that point there is no beating around the bush.
Here is how NDAs work: You sign a document saying that if the company gives you the product, you will not disclose any info about it until the date that the embargo lifts. Period.
Anyone is free to break the NDA, it is a civil contract, not a criminal offense.
However, you only get to do...
~95% of what you see out there in launch dates and benchmarks are fakes, so if you wave off everything, you are right 95% of the time.
My comment was that if we released benchmarks, I would *probably* have heard about it, but that is not 100% the case.
I am sure that we did a demo, but...
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