Hey
You seem to be an "insider" guy with great knowledge from the inside. I hope you have the answer.
We have had Apple's self-designed performance cores for a while which uses a somewhat different architectural approach with its large L1 caches and wide pipeline. Tell me if I'm wrong but I...
I think better utlization of wafers (or wafer cost) by leveraging chiplets and using 3D stacking was also amongst the goals of RDNA3.
In an economy where demand for GPUs is unlimited, optimizing your architecture for area seems a good idea, but then crypto crashed and as wafer supply became...
You seem to be a very informed persion.
If you don't mind, I'd like to take a few shots at asking you.
EVen before the introduction of V$ on CCD-s, but even more since then, I have been wondering why amd did not try to mitigate cross-CCD latency / communication with an L4$ on board of the IOD...
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