So GB206 is about 10% smaller vs Navi 44 while being slightly more efficient and having better RT. All else being a wash. I guess Nvidia still has a slight PPA advantage, GDDR7 can’t account for all of that.
GCN had terrible PPA in later iterations which had knock-on effects for efficiency of course. IIRC The memory subsystem was also pretty atrocious and caused a lot of issues getting full theoretical performance. I was under the impression CDNA still had to work around these problems despite...
You’ll have to elaborate on that for me.
My understanding is that they’re driving to a unified modular CU and ISA. Then just insert additional IP as appropriate for the target market. With GFX 9 having so much legacy baggage, it would seem prudent to use RDNA as the basis. I can’t see AMD...
This implies it’s built on the RDNA 4 ISA? That would be sooner than expected, I figured RDNA 5 at the earliest. They’ve been adding architecture features useful for AI and datacenter since RDNA 3. I figured that was their game plan, slowly expand the RDNA ISA until it’s ready. If they think...
Yup that’s always been the trade-off between speed and efficiency. In very basic terms, the closer transisters are together, the shorter wires can be. The less distance power has to travel, the less you lose to things like voltage drop-off. That’s why denser transistors = better power...
Why wouldn’t they? Silicon cost isn’t an issue for a ~70mm2 die and 2nm shouldn’t cost much more than N3P while offering bigger performance improvements. IIRC it may offer better yields longterm as well. N3 pushes FinFet to the absolute limit. Which is why it had issues and offers below-average...
Agreed, IPC won’t be the focus but I still expect above average single-core gains. Zen 4 was a very similar situation. Built on Zen 3’s new core and ramped everything up to 11. The final result was 25% higher single-core performance and only half of that was IPC (13%.) Huge clock-speed bumps and...
Shouldn’t be a need. All of them will be using the same packaging this time, similar to whats in Strix Halo. That’s the only reason Halo had a different CCD this time. All vanilla CCD’s are equipped with TSV’s for 3D cache so I doubt that changes.
I don’t see why they’d need a 3rd CCD type...
That’s not how it works from what I understand. AMD’s semi-custom group will make anything you want for the right price. One question I have is if Sony and Microsoft are responsible for ordering wafers directly from TSMC and basically having their own WSA contracts?
CCD? Probably two.
- Zen 6
- Zen 6C
IOD? Probably four.
- Desktop
- Server
- Medusa (Laptop)
- Medusa Halo
There’s rumors of two desktop IOD’s. A fancy new 3nm one with the Neural Engine and maybe more CU’s. Plus a cheap 6/4nm one for low-end products that’s stripped down. Not sure, we’ll see.
I mean Intel has separate GPU tiles on their mobile SoC’s now. Other issues aside, EMIB seems quite affordable now that it’s at volume. I don’t think it’s far-fetched AMD follows suit before long. Those super complex SoC’s are quite difficult to make apparently. Separating more things out of the...
I understand they gotta prioritize server but abandoning chiplet consumer GPU’s may be foolish. I assumed the plan was to share GPU chiplets with laptop. Future laptop chips could then share CPU and GPU dies with desktop. The only custom die would be an IOD of some sort. Probably with the GPU...
MI400 then. Just theorizing about why they’d use such a complex package for consumer products. Perhaps they’re trying to reuse a package design made for server? Yeah it might cost more but the R&D was already paid for.
Would also open up some options for die sharing in certain markets. Slapping...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.