Geekbench needs to measure multi-threaded memory bandwidth (in both the "Memory Performance" and "Stream Performance" sections. I have routinely ignored the overall Geekbench score and looked only at the first two sections (integer and floating-point) because of this problem.
Since Nehalem...
As Anand said (see http://www.anandtech.com/show/7085/the-2013-macbook-air-review-13inch/4 ) Intel has been rather stingy on die photos this time around.
So just for fun, I made an image that shows how I think the GT3e die would look:
The image is based on:
1. The VR-zone package...
Oh, darn :oops: Sorry, I wasn't paying attention somehow.
Yes, this raises an important point, which is: how can we get all 1,155 pins to contact sufficiently well when all the pressure to make those pins contact has to be delivered through the die!
I kinda think IDC was counting on the LGA-1155 socket's pins to provide the needed springiness. Since there are 1155 of them (duh :rolleyes:) and they're not really designed to be used as springs per se, I imagine getting the right contact pressure at all four corners is pretty hard.
Intel...
Thank you for your persistence and following through with these experiments.
By the way, two photos both read (in yellow lettering) "Entire CPU package (including IHS adhesive)". The second of these should instead read "Entire CPU package (with paper shim)" or something like that.
Yep -- and high-end dual-socket Xeon workstations too!
Upgrading and Analyzing Apple's Nehalem Mac Pro (Anand, 2009 July 13)
"No lid, all Nehalem."
Note Anand's trouble with getting the HSF mounted safely onto the replacement CPUs with heatspreaders. He had the reverse problem that...
I noticed that the Intel Sweden version Ivy Bridge die photo shows a slightly different layout (for example, in the size of the gap between the cores and the L3 cache) and also has fewer interconnect layers. Compare it to the official Ivy Bridge die photo from April 2012, and you can see that...
If true, that would agree with the CPU World article listing Haswell die and package variants which was met with some skepticism in this thread last month over the large die needed for 4 cores + GT3 and the inclusion of a single-channel memory controller variant. (I however believe it's pretty...
Yep. Your analysis was great, by the way, and gave us a lot to think about months before we had the hard numbers on Ivy Bridge. Also, you gave great Haswell predictions which still look pretty good (we have nothing solid yet on the 4c+GT3 variant, but the square die seems likely)
Okay, here is a preliminary labeling of the Haswell die shown in this Flicker post by "IntelFreePress" dated 2012 Sep 10th. Click the yellow bar to embiggen.
Perhaps you'd like to identify more of the parts. :D
Wow... that image is available in a 12-megapixel version! It is at this Flicker post by "IntelFreePress" dated 2012 Sep 10th. On the Flickr page, use the "View all sizes" link to access the huge version.
image removed
Let's take pity on the bandwidth challenged, shall we?
admin allisolm...
I forgot how many of these I scraped up last week. Here's another one:
which is in several blogs and re-posts apparently originating with this post by Intel on their Google+ page and dated 2012 Sep 13th.
This has the same new core layout, the GPU with 20 execution units, L3 cache with...
There is one other Haswell die photo that appeared in news posts at about the same time. Here it is:
I found it in this article on newelectronics.co.uk
My analysis of this image is the same as the one in the BBC article: 4 cores with a new layout, GPU with 20 shader cores and a different...
About that empty space in Ivy Bridge: Refer to the Ivy Bridge die sizes article again.
The "biggest" Ivy Bridge is the HE-4, 8.141 x 19.361 mm and has 8MB of cache. The Ivy Bridge HM-4 still has 4 cores, but only 6MB of cache, and is only 7.656 mm wide, about 1/2 millimeter smaller. Clearly...
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