I wanted to elaborate; right now edc and adaptive clock both operate, but not as a single field. EDC does not command the voltage step. It drops bins upon vdroop, but doesn't have a facsimile cpu bin voltage stretching feature. It could have a normative voltage field offset just as adaptive...
There was a mention of IF max clock. 2400 it was. Looking in the same mindframe with 1.6:1 ratio, it enables 7200MHz ddr(double data rate). Btw, 3200/1066 equates 1.5, sorry about that.
Do OEM's set IF clock? I don't know if it were a thing. We have discussed this with seronx, the result was IF could run @1066 to keep this 3200MHz memory rate. Comparatively with zen 3, the generational gap is present. Also, 2400 is likely, I haven't seen its mention.
It is a matter of whether AMD just patched adaptive clock, or went the whole profile bin tuning route. You can have wee bit of clock stretching at the turbo bins, however it is blind faith to assume that is how mobile thriftiness is supposed to work. Either the bins need near voltage threshold...
Ryzen Master provides you on pointers as to how you can revert back to basics. Generally, even 3900X has a correspondingly low base setting(90A EDC - equal to 60A on 3700X). The gist of the matter is that EDC provides another safety net which should fall just shy of the PPT limit.
Also, PBO is...
When discussing designated TDP performance, I think a major portion of the emphasis is on task power per stock TDP. This is an area in which major contenders take a heavy blow by the underdogs(Apple vs. Qualcomm & Intel vs. AMD). Intel for instance cuts short the frequency bins when running...
Hi,
I just found this on Reddit which I happened to consider to be useful for comparison's sake between EDC vs. PPT settings. Normally, you would think power regulation via PPT should fare better. That is more than likely, not to be the case. PPT helps relieve socket TDP for untampered...
In my last contribution, in this video doctor Aneesh goes on to differentiate between gate devices. If you scroll around 15:30, Finfet is the upside down perpendicular version of a double gated transistor and the gate at the end of the road is a gaafet.
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