but it's 7 tiles high. Not saying 42 (28+2*7) cores will be done, but it could be (check out that lonely core in the bottom tile, so a core could probably be added to the top tiles as well.
Intel said that with Tigerlake, they did not focus on IPC improvements (i.e. larger ROB etc.) . Instead I think they focused on making it more efficient (even without better transistors) by overhauling everything. (i.e. what is normally called "CDyn optimization" by the designers). I.e. the...
- dual core Skylake GT2 / 24 EU is 98 mm2.
- Cannon Lake IA core may have full AVX512 units
- Gen10 architecture, more EUs.
- remaining IO circuits likely don't scale down much.
- AVX512 really seems like a BIG mistake... maybe already AVX256 / FMAC was.
- new cache hierarchy seems ok, but not worth the effort
- mesh is good for the future and for higher core counts, I support making that change.
- IIRC with the 3-memory-channel in Nehalem-EP, some RAS features only...
Skylake-X data sheeet:
http://www.intel.com/content/www/us/en/products/processors/core/6th-gen-x-series-spec-update.html
if the data sheet is correct, then Skylake-X will indeed have FIVR.
Note that they got the cache size wrong in the beginning (copy/paste error from Broadwell-E).
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