Well, I do wonder if you have over-read the counter struct. The outer dimension of the 2D array seems more likely to be different counters of a particular type, while the inner dimension is the counter data of a particular block. This is more reasonable, and all the data points match what is...
I'm certain that the HBM1 standard is publicly available, and has no single word on clamshell-like thingy. Let alone the fact that 1024-bit interface is comprised of eight 128-bit channels. Moreover, that's not really interleaving but more of "share command bus but split DQ".
Likely both can be used together, since the chipset is seemingly just a hub of I/O which takes a x4 connection. The clock gen, SMBus and BIOS stuff are moved onto the SOC already. It is possible that the x4 connection can be split into four x1 GPP either.
No. Richland is a revision of Trinity, and fitting one chip into socket infrastructures does not equal to making two infrastructures compatible. Let alone that Carrizo doesn't ever announce an SKU that fits into FM2+.
You'll need a unified scheduler for such a configuration. That's said an ALU sharing a port with a store AGU doesn't sound unreasonable.
P.S. It seems AMD still doesn't bother to give store data bus its own issue port, ehm.
Yeah. The "real" northbridge is between the core pairs, with the memory controller and the GMC block, IIRC. The rest on the left is the I/O complex and all the GPU and multimedia related stuff, which is called Graphics Northbridge.
8 modules means an 8192-bit interface of 1 to 2 TB/s of bandwidth. You may just get served well with a generic DDR memory stick after all and get that power consumption off package. HBM itself and the assembly isn't cheap but still bleeding edge now either.
May 7 Analyst Day.
Needs of VRAM could grow. Needs of system memory could grow too. Yet today's HBM cannot cover both the needs on its own at a nice rate of capacity per dollar, especially if you are expecting it to appear on the BOM of more mainstream variants instead of stuff like the alleged HPC APU.
Maybe...
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