Recent content by repoman27

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Discussion Apple Silicon SoC thread

Apple paid half a billion for Anobit in 2011 so they could own their memory signal processing chips. They didn't add the SerDes and PCIe interface until much later, when they finally integrated their custom SSD controller into the A and M-Series SoCs. And I'm sure they paid Synopsys or whoever...
- repoman27
- Post #9,706
- Mar 19, 2025
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

The extra die in the NAND packages is Apple's custom Memory Signal Processing (MSP) chip: The EE Times Japan article was written by Hiroharu Shimizu of TechanaLye Shimizu (@techanalye1 on X / Twitter). I'm pretty sure he knows what he's talking about, although some degree of nuance is likely...
- repoman27
- Post #9,702
- Mar 18, 2025
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

The M3 Ultra has a 1024-bit (64-channel) LPDDR5-6400 memory interface. There is no inherent issue with dual-ranked LPDDR; it's actually quite common. Because the M-series memory interfaces are stupid wide, dual-ranking generally isn't necessary. Also, the DRAM is on package, which places...
- repoman27
- Post #9,624
- Mar 7, 2025
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

According to Kurnal's composite image, it looks like the R1 is 3 active tiles, 6 embedded silicon passives, and 8 dummy tiles. The smaller tiles flanking the main tile look like memory dies, and the d2d interface looks an awful lot like UltraFusion. So probably bumped InFO-LSI again, or possibly...
- repoman27
- Post #7,628
- Jul 4, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

The entry level M2 Max Studio dissipated up to 145 W, while the fully equipped M2 Ultra version could pull 295 W. The highest power consumption for an M3 Max in a laptop isn't necessarily the highest power draw for an M3 if you were to let it off the leash. But you can't just stack two SoC dies...
- repoman27
- Post #7,627
- Jul 4, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

I wonder if the R1 was bumped (InFO/CoWoS) or bumpless (SoIC)? Regardless, it was Apple's first crack at a truly disaggregated design with 11 tiles, although I'm not sure all of them are active.
- repoman27
- Post #7,625
- Jul 3, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

Meanwhile, I only recently acquired an A to C cable, because I wanted to back up some older computers that didn't have Type-C ports to a portable SSD and didn't trust the dodgy, not even remotely to spec adapter that came packed in with the SSD. How did you end up with a dozen A to C cables and...
- repoman27
- Post #7,526
- Jun 25, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

The M-series chips have integrated SSD controllers that use PCIe lanes for transport between the SoC and the NAND packages. Each package supports two NAND channels and is connected to the host by a single PCIe Gen4 lane. The M1/2/3/4 have 2 PCIe lanes dedicated to SSD functions and support up...
- repoman27
- Post #7,525
- Jun 24, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

I will. It'll probably look very similar to the current M2 Pro Mac mini. The only difference will be that the SSD interface will be limited to the equivalent of two PCIe Gen4 lanes and probably 2GB capacity due to the lower number of channels. I don't see any reason why Apple would omit the...
- repoman27
- Post #7,519
- Jun 24, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

USB4 is based on Thunderbolt 3, however there are minor differences in signaling rate, encoding, and tunneling protocols. Thunderbolt interoperability is optional for USB4 devices. In other words, you can in fact make USB4 hosts / devices that will not work with Thunderbolt 3 hosts / devices...
- repoman27
- Post #7,518
- Jun 24, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

So while I agree that the 24-inch iMac design is stupid in so many ways and represents a major regression from the Intel based iMacs, Apple has never made a Mac without a headphone jack: I also think a lot of people use dongles because they don't realize that Type-C ports are still USB ports...
- repoman27
- Post #7,498
- Jun 24, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

I think something may have gotten lost in translation with the Geekerwan "overclocked" comment. LPDDR5X is just higher clocked LPDDR5. Micron makes no distinction between the two in their datasheets, parts catalogs, and part numbering schemes. From teardowns, we've seen the part numbers for the...
- repoman27
- Post #7,460
- Jun 21, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

You can't expect me to notice something that obvious. 🤣 Based on that, I measured 13.10 mm x 12.71 mm = 166.5 mm², which is right in the same neighborhood of what y'all came up with already. The Thunderbolt and PCIe blocks are super easy to pick out. I didn't spend much time on this, so...
- repoman27
- Post #7,424
- Jun 19, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

How are y'all getting die size estimates when this is the first N3E chip, uses different libraries (2-1 finFLEX and 3-2 finFLEX), and is based on new microarchitechtures? What feature sizes are you using to determine scale? GPU cores? I wouldn't be surprised if die size did increase given the...
- repoman27
- Post #7,418
- Jun 19, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

Lol! Reading quickly through the thread I thought I saw SMT, but it was SME. Totally different, disregard.
- repoman27
- Post #6,688
- May 8, 2024
- Forum: CPUs and Overclocking

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