Recent content by roger_k

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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

That is a fair remark, albeit a bit removed from discussing CPU architectures and developments among enthusiasts. I equally have no interest in the x86 ecosystem, Windows-based hardware, or RISC-V, but I still like learning about what is happening in the tech market because I am curious about...
- roger_k
- Post #13,577
- Jun 10, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Yeah, that is very obvious. Not sure what these things have to do with each other. You can have great end-user experience and high software quality in a closed ecosystem and you can have total crap in an open ecosystem. Besides, which “open” ecosystem are you talking about? Most of the stuff...
- roger_k
- Post #13,575
- Jun 10, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Law of large numbers is not the right term here, indeed. I'd describe it more in terms of diminishing returns. A more interesting point is what you say about relative vs. absolute value increase. I think we will have to adjust in the future to use absolute improvements more. Expecting consitent...
- roger_k
- Post #13,563
- Jun 10, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Apple has been delivering consistent year to year performance improvements. Apples M3->M4 transition alone is comparable to Zen4->Zen5 in absolute performance increase. I too think that AMD has been making great progress with the Zen family. I don’t see however how their momentum is more sizable...
- roger_k
- Post #13,554
- Jun 9, 2024
- Forum: CPUs and Overclocking
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Question Geekbench 6 released and calibrated against Core i7-12700

Of course this is a nonsensical result. It is equally as nonsensical to cherry-pick a known (and well understood!) limitation of a test and conclude that all results must be void as a consequence. Benchmarks are not some mystical things, they are well-studied, and mostly understood software. Any...
- roger_k
- Post #405
- Jun 6, 2024
- Forum: CPUs and Overclocking
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Question Geekbench 6 released and calibrated against Core i7-12700

Cinebench R23 is a benchmark of SIMD throughtput and L1 cache bandwidth. It's as useful for assessing general CPU performance as someone's love of pizza is indicative of their knowledge of the Italian language. The 2024 version is barely any better. The only reason why Cinebench kind of works...
- roger_k
- Post #392
- Jun 5, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Which is why compares across multiple results to quantify uncertainty. It works, even if the individual results are unreliable. There is no doubt that Anandtech results are more accurate per measurenment, they are still a single number which fails to capture the variability inherent to these...
- roger_k
- Post #12,906
- Jun 4, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

And I have seen power consumpion of M1 at around 5 watts (3.2Ghz) and M4 at aroudn 7 (4.05 Ghz). So their M4 results I can agree with, the M1 strikes me as extremely low (incidentally i see 3.25 watts when more than one thread is active and the M1 core is runnign at 2.7Ghz, so maybe that's the...
- roger_k
- Post #12,794
- Jun 3, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Given the variability in the results and how sensitive they are to external factors I don't trust point estimates anymore. Just a 100Mhz clock difference can have a massive effect on IPC estimation (e.g. given a score of 11 points 3 Ghz vs 2.9 Ghz give you 3% difference in IPC!). That's why if I...
- roger_k
- Post #12,789
- Jun 3, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

It was around 5 watts for M1, it is around 7 watts for M4. Let's say 50% increase. Looks bad on paper, until we remember that these are sub 10 watt cores. I'd say they have a problem once they need to raise the wattage past 12 watts per core. Until then they are fine. Which CPU runs at peak...
- roger_k
- Post #12,779
- Jun 3, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Maybe it’s time to put this argument to rest? In the last 4 years Apple had more ST gains than any x86 designer, and their rate of improvement actually accelerated with M4. Yes, some of those were achieved by increasing the power consumption (just like anyone else does). There is no evidence...
- roger_k
- Post #12,595
- Jun 3, 2024
- Forum: CPUs and Overclocking
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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

“IPC” depends on the workload, and I think it would be good to discuss it as such. Looking at GB6 subtests, M4 improved iso-clock performance between 0% and 30% (this is discarding tests that benefit from the new matrix hardware). In the few sub tests where the iso-performance did not improve...
- roger_k
- Post #12,592
- Jun 3, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

Different functional blocks, optimized for different purposes. The GPU is least specialized (and least efficient), the NPU is most specialized.
- roger_k
- Post #7,241
- Jun 2, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

I only tested the P-core SME, single-threaded. The E-core should add another 25% I think (don’t quote me on that though). SME also has this weird 1-bit “matmul”, haven’t had the chance to test it yet.
- roger_k
- Post #7,237
- Jun 1, 2024
- Forum: CPUs and Overclocking
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Discussion Apple Silicon SoC thread

I am getting 250 GFLOPS (FP32) doing vector FMA on M4's SME unit. The hardware is, in principle, capable of 2TFLOPS, but there is not enough register file bandwidth, which means that you are limited to 2x 512b SIMD slices out of the available 16x. If Apple cares about vector performance, they...
- roger_k
- Post #7,232
- Jun 1, 2024
- Forum: CPUs and Overclocking

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