Recent content by Sohcan

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Intel says 32 nm on track for late 2009

Hey, I resent that! :) I co-authored paper 3.4 in the Microprocessor Technology session (Dynamic Frequency-Switching Clock System on a Quad-Core Itanium Processor). But yeah, the conference did turn out to be much more university-heavy than usual.
- Sohcan
- Post #3
- Feb 5, 2009
- Forum: CPUs and Overclocking
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Nehalem: AMD's design!

Eh, maybe I'm just a cynic because I focused on architecture in grad school and had switched to circuit design by the time I finished because architecture opportunities in the industry are rare. But I'm definitely not the only person that feels this way...keeping in mind that I consider "new"...
- Sohcan
- Post #33
- Aug 21, 2008
- Forum: CPUs and Overclocking
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Nehalem: AMD's design!

Hell, the nCUBE/2 had an integrated DRAM controller and I/O fabric (with 14 links supporting up to 8096 processors)...in 1991. :) And as far as core microarchitectures, most of the really exciting stuff was established in IBM's mainframes in the 60s. Honestly, there's not much architecturely...
- Sohcan
- Post #23
- Aug 20, 2008
- Forum: CPUs and Overclocking
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Why are the CMOS process sizes set the way they are?

I'm not an expert, but despite that Intel, AMD et al develop their processes independently, they do contract out to third-parties for tools and equipment. Having standard node sizes decreases the cost in using third-party equipment. Long channel fets are common in analog and tricky circuits...
- Sohcan
- Post #4
- Jul 23, 2007
- Forum: Ask a Technical Professional
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Can some explain the difference between Digtal and Analog Circuits?

??? I never said that analog IC is dead. On the contrary, I do mixed signal design in another area that requires a lot of analog components, microprocessor clock system design. However, the fortune cookie was extremely unusual, no?
- Sohcan
- Post #13
- Mar 22, 2006
- Forum: Ask a Technical Professional
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Can some explain the difference between Digtal and Analog Circuits?

Funny story: Not too long ago, I was at lunch at a Chinese restaurant with people from work. When we got our fortune cookies, one of my coworkers got a fortune that read (I'm not kidding) "Digital circuits are made of analog components". We figure that a disgruntled, laid-off analog IC engineer...
- Sohcan
- Post #9
- Mar 21, 2006
- Forum: Ask a Technical Professional
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Infinate AMD processor speed?

Making a processor work at some target frequency requires more than just making circuit paths operate faster...timing is more complex than that. Latches (or flip-flops, depending on the methodology used) are sequencing elements that "store" values at the boundaries of pipeline stages...for...
- Sohcan
- Post #6
- Mar 25, 2005
- Forum: Ask a Technical Professional
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processor size, features, and speed...why do they limit themselves?

Actually, the power density of the L3 cache in Montecito is extremely low...the 24 MB L3 consumes less than 5% of the total chip power (4.2 Watts). There are large opportunities for power reduction in higher-level caches using architecture and circuit techniques. Just so that Patrick doesn't...
- Sohcan
- Post #28
- Feb 7, 2005
- Forum: Ask a Technical Professional
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RAID 1 for your CPU and memory?

Yep, it's often called lockstep. IBM's G4-G6 processors (no relation to IBM's PowerPC G5 or Motorola's G4) in their zSeries mainframes have dual pipelines that execute the same instructions. At the end of checkpoint periods, the state of the two pipelines are compared, and if they mismatch...
- Sohcan
- Post #13
- Oct 22, 2004
- Forum: Ask a Technical Professional
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CPU caching scemes...

Caches can be blocking or non-blocking...a non-blocking cache allows multiple requests to be issued, and can service and complete misses out-of-order. The issue at heart is determining, as data come back out-of-order, which data is for which request. They're pretty important to performance for...
- Sohcan
- Post #4
- Sep 10, 2004
- Forum: Ask a Technical Professional
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itanium 2 with 24 mb cache?

"Only the paranoid survive." Intel has numerous contingency plans...more than a year or two out, the roadmap gets hazy. These are the questions only time will resolve. :) I don't know about mainstream rendering apps, but Itanium 2 reportedly excels at raytracing...benchmarks with POVRay have...
- Sohcan
- Post #21
- Aug 31, 2004
- Forum: CPUs and Overclocking
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itanium 2 with 24 mb cache?

Transistor per transistor and die area per die area, cache is much "cheaper" than core logic, from a basis of design effort, power consumption (static and dynamic), and performance ROI. Cache has a transistor density close to 10x higher than core logic, especially for higher-levels of cache...
- Sohcan
- Post #18
- Aug 30, 2004
- Forum: CPUs and Overclocking
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VLIW Processors - Transmetta

OOOE universally refers to the "second-generation" superscalar processors that can execute instructions that occur later in the program order that others. The processors I mentioned, among others, are always called in-order. In-order processors do not need to support re-ordering; they are...
- Sohcan
- Post #20
- Aug 18, 2004
- Forum: Ask a Technical Professional
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VLIW Processors - Transmetta

PA-RISC is a sequential RISC architecture...the current PA 8x00 series is an out-of-order implementation. The Itanium 2 core pipeline is relatively simple...this is the opinion that I've heard many times from other architects and circuit designers on my team who have had long experience with...
- Sohcan
- Post #14
- Aug 15, 2004
- Forum: Ask a Technical Professional
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future cpus: x86 to EPIC possibilities?

Sure we do branch prediction. :) Itanium 2 has a rather sophisticated two-level local history branch predictor, with a large dedicated branch history backing store, return stack buffer, and perfect loop predictor.
- Sohcan
- Post #14
- Jul 12, 2004
- Forum: Ask a Technical Professional

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