In my limited RAM overclocking experience, I've found tons of errors with HCI while memtest86 was coming up clean. Might as well use multiple tests just to be safe.
wat
It would be fascinating to see what Intel / AMD could do with a high-performance RISC-V implementation. AMD is currently a member of the foundation - they could be playing with the idea.
512 bit arithmetic would be very expensive to implement. An adder that large would prove very expensive and would have a latency of at least 2 clock cycles, and a fully pipelined multiplier would be both 64 times as large as a similar 64-bit multiplier. With double precision floating point you...
Imho, 14nm+ refinement has been better for us PC guys than any recent shrinks. We actually got a nice ~8% frequency bump to maximum attainable ambient overclocks, rather than a regression as with 22nm and 14nm. We shall see if 14nm++ is a smaller improvement due to diminishing returns...
Speaking anecdotally, Intel seems to give unspecified flops ratings in terms of double precision. Not that it makes much sense here since they'd want a higher number for their shiny marketing slide, but there is perhaps hope it will be fully enabled.
Given the Intel process slides posted a while back showed 14++ being the same improvement over 14+ as 14+ was over 14... I wonder if we'll be seeing 5.6 GHz overclocks possible on CFL-S. Doubt it, but looking forward to finding out this August.
A wide machine is very rarely going to be firing on all execution ports every cycle (or issuing the maximum number of ops per cycle etc). I don't think failure to fill an execution port would be referred to as a "stall", so you're pretty much always going to have room for some SMT scaling even...
I'm under the impression fo4 isn't as useful a metric these days. Just using the estimated process time per fo4(<10ps) you get an fo4 delay of 40+ for modern Intel architectures, whereas 20~25 seems like a more reasonable estimate. I think this is due to the increasing (about half now?)...
Was still curious about this, and found some Intel papers confirming the presence of double frequency ALUs in Prescott and Cedar Mill. The removal of support for dependent operations in consecutive 1/2 cycles rather defeats the point though. If they it down from 4 to 2 or even 1 ALU ops/cycle...
I was under the impression it remained, but the 1/2 cycle bypass was removed to make room for the 64 bit addition on the critical path.
Interesting, although I wonder where he got his information from. The lack of the fast bypass would make it indistinguishable to an outside observer...
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