An otherwise great, well-written, clear and cohesive post, but your memory is off here - my Q9450 had 12MB of L2! While that wasn't an early C2Q, it wasn't an extreme edition either. It kept up admirably until I replaced it in 2017, after nine years of service.
Yeah, I don't find that rumor plausible either (doesn't fit AMD's roadmap, and bringing forward a design on that scale seems extremely unlikely). But those would be the reasons, not "the free capacity is 5nm LP, not HP!". Some people seem to assume that if free capacity exists even for a moment...
Is it at all likely that TSMC 5nm LP is made on different equipment than AMD's reported 5nm node? I'm not saying reconfiguring (parts of) a fab configured to 5nm LP to AMD's 5nm "HP"(?) would be trivial, but it doesn't sound impossible either. It's not like they're building a new fab for this node.
Isn't AMD supposedly going to use a somewhat custom 5nm node according to some rumors? Unlike 7nm it is at least conceivable for this to happen given AMD's massive growth recently (especially with upcoming datacenter growth). Not saying it's true, but there are definitely less plausible rumors...
Yeah, I was thinking the same thing back when they first showed that block diagram, that AM4 has no way to connect more than x16 + x4 to the CPU no matter what you do. As such you're likely right that one of those x4 blocks is repurposed as a chipset uplink - after all, AMD chipset are just PCIe...
According to AMD themselves, mobile Renoir has two storage blocks, each of which can be either an x4 NVMe drive or some unknown SATA configuration. It might be possible for one of them to be x2 NVMe and SATA I suppose, but at least according to AMD's own block diagram of mobile Renoir, that's...
Power numbers like those are typically for logic, not I/O, so power scaling for an I/O die is likely to be significantly worse than that. Same for area, and performance doesn't matter much for that application.
Bespoke CPU/APU chipsets is a terrible idea, it would utterly decimate the selection of motherboards available for APUs. It would for all intents and purposes kill DIY apu sales, relegating them to pre-builts alone. Plus it would removeany upgrade path for APU buyers. Two platforms (HEDT + MSDT)...
They're not going to put a GPU in the IOD, there's no point - a meaningful GPU would be too big to fit in the IOD (remember, I/O doesn't shrink well with node changes, so the IOD would be big even on 7nm), and there wouldn't be any point to adding a stripped-down one given that their customers...
I got that, it's just that they still needed to add the lanes + connect the pins to make the x8 GPU connection into an x16. So there are changes to the pinout of Renoir desktop APUs compared to previous ones. As for NVMe, as you can see from the slide in my previous post, mobile APUs have two x4...
They might have incorporated the necessary pins for x16 in the mobile package from the beginning and simply not populated them until now; the size and cost difference would be minimal. As for desktops, remember that desktop and mobile packages are completely separate pieces of hardware, and AMD...
Yeah, that would be very interesting to see. Though remember that AT does their phone power testing with a fan blowing onto the back of the phone, and while thermal transfer between a phone SoC and its back is anything but perfect, there is nonetheless a dramatic increase in surface area there.
Doesn't the 4300U have cores enabled on just the one CCX anyhow? This would likely look very different if it was a 4700U or 4800U. Or even a 4500U or 4600U.
Even with some added airflow, being able to dissipate 5W from the silicon die alone is downright stunning, even if it's bouncing off TjMax and throttling constantly. That's the kind of thermal envelope that makes phones overheat, after all, and they are quite a lot bigger than that die. Of...
Not a pin limitation, a die PCIe controller limitation. Picasso/RR had x16 + x4 PCIe, of which the former was divided into x8 for the iGPU and x8 for PEG/GP PCIe. Desktop APUs don't populate the pins for the last 8 PEG lanes; desktop CPUs don't populate the iGPU graphics output pins. Socket pins...
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