Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

poke01 · Apr 12, 2024

SiliconFly said:
You can compare nodes based on their products only if both are exact same (even the libraries have to be very similar). Otherwise it makes no sense.

You can compare products in the same class that use the node without any excuse.

Lunar Lake and M3 both use 3NB and target ultra books and tablets. In fact this the most fair comparison between Intel and Apple for the first time! So we gather a lot information, 2024 is a very exciting year for CPUs/SoCs

SiliconFly · Apr 12, 2024

poke01 said:
You can compare products in the same class that use the node without any excuse.

Lunar Lake and M3 both use 3NB and target ultra books and tablets. In fact this the most fair comparison between Intel and Apple for the first time! So we gather a lot information, 2024 is a very exciting year for CPUs/SoCs

Again, not really. Remember, it still has an active interposer (intel base tile). It skews the graph.

"Most fair comparison", I agree, cos it's inherently subjective. But a direct 1:1 comparison can never be 100% accurate.

Ghostsonplanets · Apr 12, 2024

SiliconFly said:
Again, not really. Remember, it still has an active interposer (intel base tile). It skews the graph.

"Most fair comparison", I agree, cos it's inherently subjective. But a direct 1:1 comparison can never be 100% accurate.

Even if so, Lunar Lake was squarely aimed at competing and surpassing Apple M series. It's Intel x86 direct response to it. So it will be judged on whether it can hold and surpass the M Series or if It's another Lakefield.

Intel themselves have put this bar unto them by doing direct comparisons (LNL 12W = 2.5 TFLOPs. Equal to M1. LNL full power = 3.8 TFLOPs. > than M2). So they'll have to bear criticism if they can't achieve it.

SiliconFly · Apr 12, 2024

Ghostsonplanets said:
Even if so, Lunar Lake was squarely aimed at competing and surpassing Apple M series. It's Intel x86 direct response to it. So it will be judged on whether it can hold and surpass the M Series or if It's another Lakefield.

Intel themselves have put this bar unto them by doing direct comparisons (LNL 12W = 2.5 TFLOPs. Equal to M1. LNL full power = 3.8 TFLOPs. > than M2). So they'll have to bear criticism if they can't achieve it.

Ya. LNL is gonna be compared with M series a lot and it's going to be fun. Can LNL surpass M series... I doubt it cos it's a difficult hurdle. But still it's gonna be fun comparing.

dullard · Apr 12, 2024

Ghostsonplanets said:
Will Intel keep flip-flopping between TSMC and Intel Foundry?...Intel themselves have said i18A would still be behind the industry best in some metrics.

Please take a look at this chart: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41180614

As you should be able to see, Intel doesn't have the wafer capacity to go all in on 20A/18A or even Intel 4/Intel 3 at least until ~mid 2026 to 2027. So, yes, Intel will use both TSMC and Intel Foundry for quite some time.

As for your last sentence, could you please link which Intel statement you are speaking of. From what I can recall, Intel has said 18A would be roughly equivalent. See this graphic for example: Intel themselves have said i18A would still be behind the industry best in some metrics. https://www.servethehome.com/intel-foundry-operating-model-shown-with-path-to-process-leadership/

Hitman928 · Apr 12, 2024

SiliconFly said:
Again, not really. Remember, it still has an active interposer (intel base tile). It skews the graph.

"Most fair comparison", I agree, cos it's inherently subjective. But a direct 1:1 comparison can never be 100% accurate.

Where did you see that the base tile is active?

Ghostsonplanets · Apr 12, 2024

dullard said:
Please take a look at this chart: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41180614

As you should be able to see, Intel doesn't have the wafer capacity to go all in on 20A/18A or even Intel 4/Intel 3 at least until ~mid 2026 to 2027. So, yes, Intel will use both TSMC and Intel Foundry for quite some time.

I am puzzled because, Panther Lake, the next generation mobile in 26, will exclusively use Intel 18A for the Compute Tile.

Intel ships a lot more ships on mobile than Desktop. TGL did > 100M, ADL/RPL > 50M and MTL currently at 5M and Intel projects 40M by the end of this year (Combined with LNL). So I'm puzzled at how PTL will ship in volume by 26 yet NVL will go towards TSMC N2.

The only explanation, imo, is that 18A trails behind N2 and IDC choose N2 to stay competitive and at node parity with Apple, QCOM and AMD.

Hulk · Apr 12, 2024

I'm confused regarding the core-to-core latency chart in the Anandtech MTL review.

Are the 4.5ns latencies HT cores? Meaning within the same core? I'm confused.

https://images.anandtech.com/doci/21282/Intel%20Core%20Ultra%207%20155H%20Core%20to%20Core%20Latency.png

dullard · Apr 12, 2024

Ghostsonplanets said:
I am puzzled because, Panther Lake, the next generation mobile in 26, will exclusively use Intel 18A for the Compute Tile.

Intel ships a lot more ships on mobile than Desktop. TGL did > 100M, ADL/RPL > 50M and MTL currently at 5M and Intel projects 40M by the end of this year (Combined with LNL). So I'm puzzled at how PTL will ship in volume by 26 yet NVL will go towards TSMC N2.

The only explanation, imo, is that 18A trails behind N2 and IDC choose N2 to stay competitive and at node parity with Apple, QCOM and AMD.

There are plenty of explanations.

Timing (you need a chip design to match up with the node readiness),
Hedging bets (so that Intel doesn't fall into the trap again if one of their nodes are delayed),
Scheduling with other 18A customers (If Intel Foundry is really going to be a success their customers need to not be on a waiting list),
Potential differences in cost,
Wafer capacity vs. expected demand,
etc.

https://www.intel.com/content/www/u...-innovation-product-leadership.html#gs.7asadp

Expanded use of third-party foundry capacity. Intel expects to build on its existing relationships with third-party foundries, which today manufacture a range of Intel technology...This will provide the increased flexibility and scale needed to optimize Intel’s roadmaps for cost, performance, schedule and supply"

I edited my post above, but probably after you read it, so I'll copy it again:

Ghostsonplanets said:
Intel themselves have said i18A would still be behind the industry best in some metrics.

From what I can recall, Intel has said 18A would be roughly equivalent. See this graphic for example: https://www.servethehome.com/intel-foundry-operating-model-shown-with-path-to-process-leadership/ Or what Gelsinger said last year that 18A is a little bit ahead of TSMC 2nm. https://www.tomshardware.com/tech-i...els-process-arrives-a-year-earlier-than-tsmcs

That doesn't mesh with your idea that Intel thinks 18A trails behind N2.

Tigerick · Apr 12, 2024

Ghostsonplanets said:
I am puzzled because, Panther Lake, the next generation mobile in 26, will exclusively use Intel 18A for the Compute Tile.

Intel ships a lot more ships on mobile than Desktop. TGL did > 100M, ADL/RPL > 50M and MTL currently at 5M and Intel projects 40M by the end of this year (Combined with LNL). So I'm puzzled at how PTL will ship in volume by 26 yet NVL will go towards TSMC N2.

The only explanation, imo, is that 18A trails behind N2 and IDC choose N2 to stay competitive and at node parity with Apple, QCOM and AMD.

Yes, you have come to common sense. There are always few people believe what Intel OR Pat claimed but the reality is IF is way behind in TSMC's PPA. In the past, when rumored said most of ARL's tCPU going to be made by TSMC's N3B, they don't believe and said 20A is more advanced process with first to offer GAA. Turn out, Intel 20A is a short live process and they are used for low end ARL's CPU. Sound familiar, yeah, SF has been doing it with their SF3E. IF and SF are both want to leapfrog TSMC by using more advanced techniques but they are still lag behind TSMC in true PPA. That's why IF and SF are BS all the times yet still not getting any major contract.

	ARL ?	ARL-H/HX/S	LNL-MX	PTL-H	NVL-S
tCPU	20A	N3B	N3B	18A	N2

tGPU	N5	N5	N3B (Same as tCPU)	N3E - 12XE, I3 - 4XE	I3 - 4XE

SoC / PCD	N6	N6	N6	N6	N6

As listed in the table, tell me how many tiles are made by IF?

There are already some official specs of NVL-S leaked out but no core count yet. My source said NVL-S going to support 128-bit DDR5-8000, that's why I suspect the rumored 16+32 (ARL-S going to have 8+32 version next year) might be true. That require tCPU in needing more advance process than N3B. That's why I still believe NVL-S's tCPU is going to be made by TSMC's N2 process. Come back when Intel officially announced NVL-S in Q4-2026 and see which process Intel is using ? I can't wait ...

Ghostsonplanets · Apr 12, 2024

dullard said:
There are plenty of explanations.

Timing (you need a chip design to match up with the node readiness),

Hedging bets (so that Intel doesn't fall into the trap again if one of their nodes are delayed),

Scheduling with other 18A customers (If Intel Foundry is really going to be a success their customers need to not be on a waiting list),

Potential differences in cost,

Wafer capacity vs. expected demand,

etc.

I edited my post above, but probably after you read it, so I'll copy it again:

From what I can recall, Intel has said 18A would be roughly equivalent. See this graphic for example: https://www.servethehome.com/intel-foundry-operating-model-shown-with-path-to-process-leadership/ Or what Gelsinger said last year that 18A is a little bit ahead of TSMC 2nm. https://www.tomshardware.com/tech-i...els-process-arrives-a-year-earlier-than-tsmcs

That doesn't mesh with your idea that Intel thinks 18A trails behind N2.

I agree there are plenty of reasons. And those posted are very believable ones. But if 18A is releasing on volume with PTL and 18A is supposed to bring parity or better than N2, why would NVL be on TSMC?

My best guess is that density isn't at the level IDC would want. Specially if the 16+32 rumors are true. IIRC Intel 18A metal pitch is roughly the same as Intel 4.

But maybe it's just that Intel will prioritize mobile volume and thus PTL and are going towards TSMC due to volume.

Tigerick said:
Yes, you have come to common sense. There are always few people believe what Intel OR Pat claimed but the reality is IF is way behind in TSMC's PPA. In the past, when rumored said most of ARL's tCPU going to be made by TSMC's N3B, they don't believe and said 20A is more advanced process with first to offer GAA. Turn out, Intel 20A is a short live process and they are used for low end ARL's CPU. Sound familiar, yeah, SF has been doing it with their SF3E. IF and SF are both want to leapfrog TSMC by using more advanced techniques but they are still lag behind TSMC in true PPA. That's why IF and SF are BS all the times yet still not getting any major contract.

ARL ? ARL-H/HX/S LNL-MX PTL-H NVL-S
tCPU 20A N3B N3B 18A 18A-P / N2 ?
tGPU N5 N5 N3B
(Same as tCPU) N3E - 12XE, I3 - 4XE I3 - 4XE ?
SoC / PCD N6 N6 N6 N6 N6 ?

As listed in the table, tell me how many tiles are made by IF?

There are already some official specs of NVL-S leaked out but no core count yet. My source said NVL-S going to support 128-bit DDR5-8000, that's why I suspect the rumored 16+32 (ARL-S going to have 8+32 version next year) might be true. That require tCPU in needing more advance process than N3B. That's why I still believe NVL-S's tCPU is going to be made by TSMC's N2 process. Come back when Intel officially announced NVL-S in Q4-2026 and see which process Intel is using ? I can't wait ...

Yes, that's the question. If 18A brings unquestionable leadership, why is the Lion Cove successor still using external for the compute tile?

PTL bringing Compute and iGPU-U tiles to Intel was a sign of confidence in the Intel Foundry manufacturing prowess and capacity. For NVL to go TSMC once again is weird.

dullard · Apr 12, 2024

Ghostsonplanets said:
why would NVL be on TSMC?...

I just answered that here: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41190543

Intel doesn't have capacity. Intel doesn't have capacity. Intel doesn't have capacity. What part of that are you struggling with? If you need me to say it another way: Intel bought too little equipment and is maxed out on their top nodes.

Tigerick · Apr 12, 2024

dullard said:
I just answered that here: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41190543

Intel doesn't have capacity. Intel doesn't have capacity. Intel doesn't have capacity. What part of that are you struggling with?

NO, that's BS. If IF don't have capacity, then why open foundry business? You mean IDC rather send the business to TSMC than making it in house? The real reason is as I said, IF is not capable of producing NVL-S

dullard · Apr 12, 2024

Tigerick said:
NO, that's BS.

Ok your turn, I posted links showing Intel doesn't have capacity. If that is BS, then now it is your turn to show links that Intel DOES have the capacity to do it all. All mobile, all desktop, all foundry services. No handwaving or red herrings. Show that Intel has the EUV capacity to do it all on time. I'll wait.

Ghostsonplanets · Apr 12, 2024

dullard said:
I just answered that here: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41190543

Intel doesn't have capacity. Intel doesn't have capacity. Intel doesn't have capacity. What part of that are you struggling with? If you need me to say it another way: Intel bought too little equipment and is maxed out on their top nodes.

That chart is just wrong. If we were to believe it, then 18A has some volume since last year.

If Intel doesn't has manufacturing capacity, how do they plan to offer their foundry services to others?

They have Ericsson on i3, Nvidia on i3, ARL-U, Sierra Forest and Granite Rapids on i3, then ARL-H 6+8 on 20A, Microsoft on i18A, PTL and ClearWater Forest on i18A. There's also Falcon Shores on an advanced node (i3 or i18A). PTL is also mobile volume on i18A in 25/26 (And as I showed, Intel Mobile is a huge volume driver).

But somehow they're volume limited for a late 26 product? Even more a DT product, which is lower volume?

Were i18A to be using High-NA, I would understand. But High-NA is now on i14A, with i18A becoming i18AP. By late 26, Intel will have been manufacturing with EUV for 3 years.

If Intel is so booked or volume constrained that they can't manufacture their own DT Compute Tile, then how can they offer Foundry Services to others? If QCOM come to manufacture a Snapdragon SoC on i18A, Intel will say: "Sorry, we don't have the volume". I doubt so.

jpiniero · Apr 12, 2024

Ghostsonplanets said:
If Intel doesn't has manufacturing capacity, how do they plan to offer their foundry services to others?

They don't (besides maybe small fry), it's to placate "investors".

dullard · Apr 12, 2024

Ghostsonplanets said:
That chart is just wrong. If we were to believe it, then 18A has some volume since last year.

If Intel doesn't has manufacturing capacity, how do they plan to offer their foundry services to others?

They have Ericsson on i3, Nvidia on i3, ARL-U, Sierra Forest and Granite Rapids on i3, then ARL-H 6+8 on 20A, Microsoft on i18A, PTL and ClearWater Forest on i18A. There's also Falcon Shores on an advanced node (i3 or i18A). PTL is also mobile volume on i18A in 25/26 (And as I showed, Intel Mobile is a huge volume driver).

But somehow they're volume limited for a late 26 product? Even more a DT product, which is lower volume?

Were i18A to be using High-NA, I would understand. But High-NA is now on i14A, with i18A becoming i18AP. By late 26, Intel will have been manufacturing with EUV for 3 years.

If Intel is so booked or volume constrained that they can't manufacture their own DT Compute Tile, then how can they offer Foundry Services to others? If QCOM come to manufacture a Snapdragon SoC on i18A, Intel will say: "Sorry, we don't have the volume". I doubt so.

All handwaving. Not a single bit of evidence of capacity on your part. A shame. It almost sounds like you make up your posts and then believe whatever comes out of your mouth as proof of what you made up.

Note the graph mentions capacity: not quantity manufactured. The green bar on the graph is 20A plus 18A. So how does a bit of green bar in 2023 mean 18A was in volume since last year.

SiliconFly · Apr 12, 2024

Hitman928 said:
Where did you see that the base tile is active?

Slip. It's passive.

John Carmack · Apr 12, 2024

dullard said:
I just answered that here: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...akes-discussion-threads.2606448/post-41190543

Intel doesn't have capacity. Intel doesn't have capacity. Intel doesn't have capacity. What part of that are you struggling with? If you need me to say it another way: Intel bought too little equipment and is maxed out on their top nodes.

It's interesting to look back at what other people have said on this matter. The folks poo-pooing on Mizuho analysts and calling them Chicken Littles and those convinced Intel has more than enough capacity are looking aren't looking good right now.

Even though they have working product out there in some quantity, I still think Intel processes have problems otherwise they wouldn't be lagging behind in density and other metrics. They should really be comparing themselves against Samsung instead of TSMC.

repoman27 said:
Most of your post actually backs up my analysis, I think you just entirely missed my point.

I said that Intel probably needed 85 kwpm to produce 100% of their CPUs. You reinforced that by pointing out that when Intel did try to do everything on one node, they were supply constrained at around 80 kwpm. The actual Mizuho estimate for Intel 14nm in 2018 was 70 kwpm. Furthermore, roughly 7 kwpm on average of 14nm were going to modems for Apple in 2018, ramping to over 15 kwpm in 2019. So 85 kwpm on the leading process is a very generous upper bound for Intel's requirements.

ASML says 1 EUV machine is required per layer per 45 kwpm. Mizuho estimates that Intel will have > 15 EUV machines installed by 2023. Even if Intel's 7nm calls for 20 EUV layers (which seems excessive), they would have enough EUV equipment to accommodate at least 36 kwpm in 2023.

36 is a lot less than 85, however, nothing about Intel's roadmaps would indicate that they have any intention of manufacturing 100% of their CPUs on 7nm in 2023. In fact we know that the lead 7nm products, aside from some percentage of the Ponte Vecchio Xe-HPC compute tiles, aren't planned for release until H2'23. Mizuho's estimate of 20 kwpm may prove to be very close to Intel's average 7nm production in 2023. However, despite the inference that many folks on this forum seem to be drawing from these numbers, a lack EUV of equipment clearly isn't going to be the limiting factor for Intel 7nm. Intel will have enough EUV equipment for at least 36 kwpm, and 36 is a lot more than 20.

Intel is way behind. But the notion that the reason they're behind is because they didn't spend enough on EUV equipment doesn't align with the facts.

eek2121 said:
Intel disclosed their EUV output capability and projected future capability a year or two ago. While they are capacity constrained, they still have ample capacity for in-house products. They will soon also have enough capacity to handle external products as well.

Unless the information I have has changed (not likely), Intel 4 > TSMC N5*. Intel 4 is actually closer to TSMC N3*. Intel 3 is an optimized version of Intel 4.

SiliconFly · Apr 12, 2024

Ghostsonplanets said:
My best guess is that density isn't at the level IDC would want.... ...IIRC Intel 18A metal pitch is roughly the same as Intel 4.

Your best guess is wrong. Intel hasn't published 18A node characteristics yet. And you've already declared 18A to be a failure, inferior to N2 & is only as good as Intel 4. You have absolutely no idea what you're talking about. But pls don't stop. It's too much fun.

Ghostsonplanets said:
...If 18A brings unquestionable leadership, why is the Lion Cove successor still using external for the compute tile?

Again you have no idea what you're talking about. Process leadership has nothing to do with leadership in volume. TSMC has unquestioned leadership in volume.

Ghostsonplanets said:
For NVL to go TSMC once again is weird.

Ghostsonplanets said:
...why would NVL be on TSMC?

Tigerick said:
NO, that's BS.

NO that's not BS. Volume (like TSMC) for a new "open" foundry like Intel is gonna be very difficult to achieve in a short duration. TSMC already has that expertise. Intel doesn't. It's gonna take a few years to catch up.

And don't forget the EUV shortage controversy. I think it still affects Intel in some form.

dullard said:
All handwaving. Not a single bit of evidence of capacity on your part. A shame. It almost sounds like you make up your posts and then believe whatever comes out of your mouth as proof of what you made up.

I noticed that too. Sometimes interesting, but mostly hilarious. Like they say, enjoy it while it lasts.

dullard said:
Note the graph mentions capacity: not quantity manufactured. The green bar on the graph is 20A plus 18A. So how does a bit of green bar in 2023 mean 18A was in volume since last year.

Trying to answer such stuff shows you have tons of energy and patience. Much appreciated.

Tigerick · Apr 12, 2024

dullard said:
Ok your turn, I posted links showing Intel doesn't have capacity. If that is BS, then now it is your turn to show links that Intel DOES have the capacity to do it all. All mobile, all desktop, all foundry services. No handwaving or red herrings. Show that Intel has the EUV capacity to do it all on time. I'll wait.

Ok, I agree IF don't have capacity to produce Nova Lake. Thanks for your vote of confidence of IF's inability to produce. I have updated the table to remove question mark of N2 process for Nova Lake since you are so confident about IF's incapability.

And I will @dullard in the future in case we have member doubt of Nova Lake's process choice, cheers !

Ghostsonplanets · Apr 12, 2024

SiliconFly said:
Your best guess is wrong. Intel hasn't published 18A node characteristics yet. And you've already declared 18A to be a failure, inferior to N2 & is only as good as Intel 4. You have absolutely no idea what you're talking about. But pls don't stop. It's too much fun.

Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node

This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of 30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers...

www.spiedigitallibrary.org

Read first instead of following Intel propaganda

SiliconFly said:
Again you have no idea what you're talking about. Process leadership has nothing to do with leadership in volume. TSMC has unquestioned leadership in volume.

Yes, we're supposed to believe Intel will have capacity and manufacturing volume to do a vast amount of SKUs in the next 1- 2 years. But suddenly they'll lack it for NVL🤔.

Or perhaps i18A doesn't bring "unquestioned leadership".

Anyway, I'm dropping this. Let's see what reality will be. 2026 isn't far off...

dullard · Apr 12, 2024

SiliconFly said:
Trying to answer such stuff shows you have tons of energy and patience. Much appreciated.

Thanks. I remember that this forum used to have people demand proof of everything. If you state something, you prove it with a link or a known fact. But, not to pick on anyone in particular, this forum and the whole world seems to have shifted to "if I say it, it is true"--no matter what they say. This thread in particular has become an onslaught of anything no-matter-what "proves" that Intel is "stupid" or "behind" or whatever. It feels almost like the next poster will say that since it is raining in Spain, that it shows Intel is behind in chip design.

We can clearly have differences of opinion, and certainly differences in accuracy of predicting the future. But, I strive for us all to have at least a solid groundwork on what are the basic facts that we should all be able to agree upon.

FlameTail · Apr 12, 2024

For reference, here's an official slide from Intel:

jur · Apr 12, 2024

I wonder what's preventing Intel from expanding their capacity. Is there some other bottleneck besides EUV tools? They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool. This seems very irrational decision. Wouldn't it make much more sense to ramp 18A as fast as possible, especially if the process is really as good as they say. Besides, they have Synopsis, Cadence helping them with automation tool, libraries,.. and apparently also customers, not to mention internal designs that are being sent to TSMC...

	ARL ?	ARL-H/HX/S	LNL-MX	PTL-H	NVL-S
tCPU	20A	N3B	N3B	18A	18A-P / N2 ?

tGPU	N5	N5	N3B (Same as tCPU)	N3E - 12XE, I3 - 4XE	I3 - 4XE ?

SoC / PCD	N6	N6	N6	N6	N6 ?

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