N3E is also more economical, cost wise.He thinks it will be N3B, for what reason I'm not sure. I mean why wouldn't Apple want a better process that's faster and lower power?
It will with 8 Gen 6The fact that Samsung has announced LPDDR5X-10700, makes me certain we will not seen LPDDR6 supported by the next generation smartphone SoCs (Snapdragon 8 Gen 4, Dimensity 9400).
Think about it, JEDEC hasn't even ratified an LPDDR6 standard yet!
Late 2026 SoC?It will with 8 Gen 6
Well, this LPDDR5X-10700 is question is using a better 12nm process, and Samsunf advertises 25% faster speed AND 25% better power efficiency. So no power increment.It's not about speed limits so much as how a certain bandwidth is achieved efficiently.
For example, GDDR6X doesn't use the standard GDDR6 IO protocols, which means you need a different PHY on the memory controller to handle it.
If these separate, faster LPDDR5 memories are using non standard IO protocols to achieve hgiher bandwidth without exploding the power budget then it balloons the memory controller area budget to accommodate that if they support the standard IO protocol too for cheaper SKUs.
You are missing my point - if the IO protocol is non standard then it's going to have limited use except in SoC's designed for it.Well, this LPDDR5X-10700 is question is using a better 12nm process, and Samsunf advertises 25% faster speed AND 25% better power efficiency. So no power increment.
You are missing my point - if the IO protocol is non standard then it's going to have limited use except in SoC's designed for it.
Isn't Lunar Lake's on-package LPDDR5X-8533 also exclusively sourced from Samsung?Whether or not it is non standard it limits you to a single OEM for your LPDDR5X-10700. Samsung could use this for their next Galaxy for a marginal gain over the competition, but who else would be interested in being locked into Samsung as their only vendor for their (presumably) high end product - that may compete with Galaxy - unless someone else like Micron introduces an identical offering?
10.7GbpsI would caution you to be a little more careful about believing in Samsung announcements. They have previously announced a whole bunch of memory products that simply never shipped in volume.
I will believe that Samsung has a LPDDR5X module that can do 10.7Tbps when they actually have the chips in production, and available to customers in volume.
I wonder where Samsung's LPDDR5X-10700 announcement fits into this timeline
View attachment 97268
If LPDDR6 is coming to market in 2026, then LPDDR5X-10700 has to come to market before that, or it doesn't make sense.
Have you ever thought about 10core would be named as X Plus? Guess not, I have, that's why I said 8 core might be named as X standard model.Have you heard of the Snapdragon X Plus?
- X Elite with 8 cores might not be correct naming...the thing is the launching date is same as 8 Gen4, could X without Elite be using the same SoC as 8 Gen4??? And 8 cores SoC could be 2+6 Phoenix cores?
| X | X Plus | X G2 | X Elite G2 | |
|---|---|---|---|---|
| Model No. ? | SM8750 Pakala | SM8380 | S1080 Kaanapali | SM8480 Purwa ? |
| Node | N3E | N4P | N3E | N3P ? |
| CPU Arch | Phoenix | Phoenix | Pegasus | Pegasus |
| CPU Counts | 2 + 6 | 10 | 2 + 6 | ? |
| Memory | 64-bit LPDDR6 | 128-bit LPDDR5X | 64-bit LPDDR6 | 128-bit LPDDR6 |
| GPU FP32 | ~ 4TF RT | 3.8 TF | ~ 10TF RT | |
| 5G Modem | Build-In | External | Build-In | External |
I already guessed it before X Plus was announced:Have you ever thought about 10core would be named as X Plus? Guess not, I have, that's why I said 8 core might be named as X standard model.
Fine, let's wait till 8G4 is announced.I am sure you will find something to argue, feel free. I will wait until when Qualcomm announce 8G4 and X then we will see...
Now give me a desktop strix halo next (zen6) with this on CAMM modules and 256bit interfaceActual specs and stuff:
Nyo.Now give me a desktop strix halo next (zen6)
Grandpa it's gonna be 384b now.and 256bit interface
That's excellent stuff. Mainstream really needs a bus width bump.Grandpa it's gonna be 384b now.
Each LPCAMM for L6 is 192b.
Nope, if you look into the JEDEC docs that got found today it explicitly says that LPDDR6 and DDR6 are not compatible.That's excellent stuff. Mainstream really needs a bus width bump.
I do wonder what that means for consumer zen6 and DDR5 support.
Are they really gonna support 192bit LPDDR6 and 128bit DDR5 from the same controller? If not it's EOL for AM5.
3-channel DDR5 support would be fun (yeah i know, not happening)