- Mar 3, 2017
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Mmmh, good point. Maybe it'd just be better to remove it entirely and just leave the Gen/Tier/Rev. And you can bin the "AI" bit too.
Weird hypothesis, but frankly Intel and AMD always used the numbers very poorly.
Out of 9 numbers, 4 are used: 3/5/7/9. It's a generally poor system because you don't want to have many tiers(muddies the lineup), and you don't want to have lower numbers than 5. Anyone identifies i3/R3 as "bad", to the point that some noobs actually think a 2023 i3 is worse than a 2014 i7.
Frankly I think clothes did it pretty well: S/M/L/XL?
Make 4 tiers:
- Light
- Medium
- Heavy
- Ultra
But it's kind of problematic too since it's a two sided coin, you get Bigger Number Better just like you get Lower Number Worse.
I really wonder what the heck does MS expect to do out of all the pizzazz they're forcing everyone to go with.Everything is AI now.
AMD obviously took traces from what they perceived as relevant usages, and from there concluded what to support and how to support it.Could the LP cores just be stripped of all the "go fast" bits and anything else that can't be emulated in microcode and essentially be maximally efficient microcode engines instead? They could retain full isa compatibility with the performance cores.
Remember that 9 is just a late afterthought by Intel and AMD.Weird hypothesis, but frankly Intel and AMD always used the numbers very poorly.
Out of 9 numbers, 4 are used: 3/5/7/9. It's a generally poor system because you don't want to have many tiers(muddies the lineup), and you don't want to have lower numbers than 5. Anyone identifies i3/R3 as "bad", to the point that some noobs actually think a 2023 i3 is worse than a 2014 i7.
Reminds me of the older USB speed denominators, and Spaceballs' speed levels. :-PFrankly I think clothes did it pretty well: S/M/L/XL?
Make 4 tiers:
- Light
- Medium
- Heavy
- Ultra
Absolutely other way around, buffering is there to reduce signaling latencies.At a cost of a bit of latency ?
Absolutely other way around, buffering is there to reduce signaling latencies.
Everything is AI even if it isn’t.Everything is AI now.
I really wonder what the heck does MS expect to do out of all the pizzazz they're forcing everyone to go with.
Still waiting for Nutella, Lisa & Pat to do a joint presentation where all they do is a song & dance bit dressed as mariachis, complete with giant hat, singing AI AI AI AI AI AI AI AI, while Jensen looks at them laying on a couch, drinking wine and laughing like he's Jabba the Hutt.Have their stock price go up, since any mention of the word AI "Investors" throw money at it.
Memory capacity is king. Strix Halo + 64GB RAM will beat a 4090 in any AI task if you scale it up sufficiently. And for local LLMs where capacity is by far the biggest bottleneck, it won't even be close.
Strix Halo directly competes for the semi-pro market that is buying 4090s instead of RTX 6000s. Significantly slower for tasks that fit inside 24GB, but can be used for tasks a 4090 can't touch.
With a price a tiny bit higher and consumption a tiny bit higher too. Or is this irrelevant?Then it's a manner of what fits into 64 GB but not 48 GB. The W7900 already offers this, but of course that's a professional card.
With a price a tiny bit higher and consumption a tiny bit higher too. Or is this irrelevant?
Not exactly, the LP island is supposed to be invisible and transition seamlessly depending on the load.
this is literally the opposite of a traditional HMP setup.AMD will be going big.LITTLE like more or less everyone else has already done. It's just that AMD is a little late to the party.
Doesn't exist.Zen5 Refresh
4+8 premium mobile, 4+4 mainstream mobile.And also, what will the core count be per SKU for the big vs LITTLE cores?
What is and why? And in any case, what's the problem with it?this is literally the opposite of a traditional HMP setup.
YetDoesn't exist.
You're talking about what X+Y core combination (Zen5, Zen5C, Zen5LP, ...), on what SKUs? And since you're maxing out at 4+8, no Zen5LP in Strix Halo despite being mentioned previously in this thread as having Zen5LP (and 16C Zen5, which is above 4+8)?4+8 premium mobile, 4+4 mainstream mobile.
Till the universe dies to the heat death.
HMP means all cores are OS-visible and can be active together.What is and why?
It just doesn't.
Premium ultrathin and mainstream.on what SKUs?
Halo is 16c, you can't see or feel the LP cluster.And since you're maxing out at 4+8, no Zen5LP in Strix Halo despite being mentioned previously in this thread as having Zen5LP (and 16C Zen5, which is above 4+8)?
you really can't read huh.and b.L / Zen5LP will not be used on any other AMD SKU to follow (e.g. Zen5 Refresh / X3D or Zen6)?
I know. But what's your point? And you didn't answer the question: "what's the problem with it?"HMP means all cores are OS-visible and can be active together.
Yet. As mentioned previously.It just doesn't.
What about Strix Halo then? Or you're counting that as "premium ultrathin", despite 120W TDP? I guess it depends on what battery life can be expected.Premium ultrathin and mainstream.
So why was the LP cluster added on Halo 16C? Dark silicon, since the SKU is "just for fun"?Halo is 16c, you can't see or feel the LP cluster.
That's the point. LP cores have small die area so cheap, thus many LP cores can be added, thus improves MT perf at low cost, and with good perf/W.you really can't read huh.
low power clusters are invisible.
Z5LP doesn't work in HMP configs. Or at least not planned to.But what's your point? And you didn't answer the question: "what's the problem with it?"
That's a segment above premium ultrathin.What about Strix Halo then?
Isn't that obvious?Also, you're ruling b.L and LP cores on DT ever from AMD?
no?Previously you ruled it out on mobile too
to idle.So why was the LP cluster added on Halo 16C?
It doesn't work in nT workloads. Ceases to exist once app QoS priority goes up.Also, what about perf/W with MT, no need to add it for that?
Those cores only exist when you idle.LP cores have small die area so cheap, thus many LP cores can be added, thus improves MT perf at low cost, and with good perf/W.
Why would it technically not work? Kepler already explained how the OS scheduler would work.Z5LP doesn't work in HMP configs. Or at least not planned to.
You're contradicting yourself. You said Zen5LP only in "Premium ultrathin and mainstream". You're counting Halo as above that. Yet Zne5LP will be in Halo.That's a segment above premium ultrathin.
You know, MBP14" isn't a particularly thin or a sleek device anymore. It's a brick.
No. So can we have a yes/no from you on whether you think there will ever be b.L on AMD DT?Isn't that obvious?
Yes
To what purpose? Add cost to no benefit?to idle.
Why would it not work on MT workloads? That's the whole purpose of the little cores. Max MT perf, at best perf/W, at lowest die area, at lowest cost of CPU.It doesn't work in nT workloads. Ceases to exist once app QoS priority goes up.
When idle, nothing is needed, except wakeup logic. Rest is power gated.Those cores only exist when you idle.
PS, will be interesting to see if what happened in the lab predicted well enough what happens later on end customers' devices.AMD obviously took traces from what they perceived as relevant usages, and from there concluded what to support and how to support it.
See? These LP cores are part of what you call wakeup logic.When idle, nothing is needed, except wakeup logic. Rest is power gated.
Because they are distinctly slower than the main cores, and feature reduced. They wouldn't help; they would only be in the way if trying to take part.Why would it not work on MT workloads?
Yes, LP cores can be used for that too. But if you only need wakeup logic, no need for even a single full LP core, let alone multiple LP cores. It can be done with much less logic that that.See? These LP cores are part of what you call wakeup logic.
And that's why LP cores (that is, distinctly slower and feature reduced cores) aren't needed in devices which run on mains power all the time.
That's the whole point of the LP/LITTLE cores.Because they are distinctly slower than the main cores, and feature reduced. They wouldn't help; they would only be in the way if trying to take part.
What makes you think that Zen5LP is a full core? That already exists as Zen5c.Yes, LP cores can be used for that too. But if you only need wakeup logic, no need for even a single full LP core. It can be done with much less logic that that.
No. The (rumored) "LP island" is not for that. It is for low perf at low Watts. Nothing else.That's the whole point of the LP/LITTLE cores.
They are not intended for reaching the same max ST perf as the main/big cores. The big vs LITTLE cores have different purpose. Main/big cores are for max ST perf. LP/LITTLE cores are for max MT perf, max perf/W, small die area, and low cost.