Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion

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soresu

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Dec 19, 2014
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Trying to read the ARM developer documentation is an exercise in frustration.

Found something called TTBR_EL mentioned, and instead of having it immediately identified I had to go through a whole song and dance search saga to find out what it means 😱
 

soresu

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Maybe to prevent fragmentation and confusing readers? You can change the topic of this thread to something like "Future ARM Discussion".
Kinda the opposite of what I was going for.

The current title is very specific, people just kept veering off that topic, which makes it harder to find information in older posts without knowing the exact text, or going through each page 1 by 1.
 
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The current title is very specific, people just kept veering off that topic, which makes it harder to find information in older posts without knowing the exact text, or going through each page 1 by 1.
How about "index" important stuff or start of relevant discussions in this thread in the first post? That's one way, though it would be pretty cumbersome (for you but everyone else will reap the benefit ).
 

Nothingness

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Trying to read the ARM developer documentation is an exercise in frustration.
Wait until you start looking for complex points (for instance the use of barriers).

That said I'm not sure Intel and AMD documentation is any better. When an architecture becomes complex its documentation becomes complex too. That's why a fast pdf reader is a requirement to quickly search for words in the document, because the information is found in multiple places (if that wasn't the case you would end up with documents 2x or 3x larger).
 

Nothingness

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How about "index" important stuff or start of relevant discussions in this thread in the first post? That's one way, though it would be pretty cumbersome (for you but everyone else will reap the benefit ).
That doesn't work because when you are discussing a dozen of CPUs there are multiple posts discussing other things in the middle of the discussion about one core.

Imagine having a single thread for all Zen CPUs.
 

soresu

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Those custom instructions have always been added to the ARM ISA down the road. First the ones that helped with x86 emulation and supported the strong x86 memory model, then Apple's AMX that became SME.
While ARM did add some instructions like LSE2 that do help with x86 emulation, it should be noted that the lions share of better x86 -> ARM64 emulation (binary translation) performance foudn in M1+ comes from Apple's µArch itself, rather than ISA extensions.
 
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Nothingness

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While ARM did add some instructions like LSE2 that do help with x86 emulation, it should be noted that the lions share of better x86 -> ARM64 emulation (binary translation) performance foudn in M1+ comes from Apple's µArch itself, rather than ISA extensions.
It's a combination of both uarch and instructions. The store ordering is an important uarch thing, but the brain dead flag computation of x86 requires specific instructions.

IIRC Qualcomm also implemented store ordering.
 
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soresu

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Interestingly it looks like that Korean website talking about a A700 -> x900 perf niche filler called Alto might actually be on the ball if this post from gizchina is correct.




The text claims it is just a lower clocked X930 (Travis) core though, which doesn't make any sense, as I can't recall ARM ever giving a codename to a gimped core before now.

Perhaps there are wider SVE2 units in Travis (256 bit max), while Alto's SIMD ALUs are still 128 bit with less of them (6 -> 4 maybe).
 
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adroc_thurston

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The text claims it is just a lower clocked X930 (Travis) core though, which doesn't make any sense, as I can't recall ARM ever giving a codename to a gimped core before now.
Lobotomized X4 very much exists to giving it an actual name was a matter of time, really.
 

soresu

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Lobotomized X4 very much exists to giving it an actual name was a matter of time, really.
That lobotomised cores exist does not surprise me, and I do already know of codenamed lobotomised CPU cores from at least AMD in the past.

Speaking of AMD, I wonder if perhaps Alto is ARM's ode to their Zen(x)c cores?

Given ARM's highly modular CPU core design philosophy they are probably the company best set up to respond quickly to this kind of threat in the market.

If they can offer an area optimised variant of X900 that gives them significantly more IP options to present to prospective licensees.

I can certainly imagine Neoverse Vx variants at ≤2/3 area going down like a charm for their hyperscaler customers, even if the licensing costs haven't decreased that much, simply because the silicon costs in SoC development for a given area are that much higher at this point in semicon manufacturing.
 

soresu

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Confirmed!

Cortex X930/Travis has SME:



Something something ARM Lumex CSS mentioned at 29:15 in this video:

 
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soresu

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The video above was editorialised on this page from ARM's own website:


Arm’s reach across all these markets is made possible by the ubiquitous Armv9 architecture, the foundation of modern computing. Since its introduction four years ago, many of the world’s latest mobile handsets and PCs are now powered by Armv9 CPUs, bringing a range of AI performance benefits to these devices. Later this year, the new Armv9 flagship CPU – Travis – will bring double-digit performance gains, with the further acceleration of AI workloads through our latest architecture feature, Scalable Matrix Extension (SME). This will be paired with Arm’s next-generation GPU – Drage – which unlocks sustained performance for longer gaming and richer multimedia content – to deliver Arm Lumex CSS for the future of edge AI on consumer devices.
 

soresu

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Dec 19, 2014
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ARM will finally beat Apple IPC wide this year if Apple doesn’t improve this year.
Considering the claimed double digit IPC increase all they need to do is work on clock frequency at this point.

Curious to see what A730 and A530 bring.
 
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