This is true for mobile, but not desktop.my guess total node improvements will be around half compared to max possible:
-30% power
+20% perf
density allowing 12core CCDs just enough
This is true for mobile, but not desktop.
that's not the issue.well power is not an issue on desktop so I guess higher perf, same cores
Careful with that kind of thinking. You might be setting yourself up to be disappointed.
I believe in zen 6 +42.0% 😤😤😤😤 at least in mobile
I will quote my post next year, #2205 page 89 zen 6 speculation thread
Claiming 25% higher ST today, leading to claims of 40%+ tomorrow and then it is another Zen 5 disappointment LOL
fixed 😤😤
What, no Zen 60%?
Lots of those people are fanatics because you need real patience to do Cinebench runs.but lots of people seem to take those Cinebench scores pretty seriously.
That would be rather high for "leveraged cores".I would guess that desktop Zen 6 is only 15-20% higher IPC than Zen 5 ...
Higher bandwidth, lower latency IOD is one thing. There will also be higher bandwidth main memory — but not appreciably lower latency main memory.... and most of that will likely come in the form of a higher bandwidth, lower latency IOD.
Only in an iso-clock comparison at moderate core clock (relative to memory clock). Not e.g. in an iso-power comparison, obviously.In MT, I expect that Zen 6 will easily improve over Zen 5 by 50% simply due to having 50% more cores.
The 54 core monster is likely to run into memory throughput issues in the only cases where that many cores would truly make a difference, unless they have significant improvements coming in that area.
One way could be segregating the P and E cores into their own NUMA domains, each with its own dedicated dual channel slots and using their Thread Director to give the necessary hints to Windows Scheduler. It will be more complicated and will need all RAM slots to be filled but if it's the only way, they could go with it.unless they have significant improvements coming in that area.
lmao dawg that ain't flying in client.One way could be segregating the P and E cores into their own NUMA domains
Do you have a better idea on how to increase the RAM bandwidth to all the cores without going quad channel and without a large L4 cache (which Intel has so far scrapped due to unknown problems, probably cost and yield)?lmao dawg that ain't flying in client.
NUMA is a pain. NUMA is extra pain in client.
you just don't do it?Do you have a better idea on how to increase the RAM bandwidth to all the cores without going quad channel and without a large L4 cache (which Intel has so far scrapped due to unknown problems, probably cost and yield)?
just not enough volume to make it cheapwhy is quad channel so expensive? die size or other?
Separate memory channels require more traces on the motherboard. That in turn may require more PCB layers which increases costs further. Mobo OEMs have experienced similar challenges with implementing PCIe5 on consumer motherboards.just not enough volume to make it cheap
more money on boards and DRAM for limited to nonexistent gains on msdt sockets.why is quad channel so expensive?
Nehalem went tri-channel in 2008. No followups since then (IIRC), right?why is quad channel so expensive? die size or other?