That's what people claim. But the actual impact on particular games (or other workloads) has never been measured.A dual vache CCD still has the inherent cross CCD penalty. It doesn't really help.
Small core complexes are an enabler of low latency of the L3 caches.Instead what you should be asking for, is an overall larger CCD
I don't think that's true.That's what people claim. But the actual impact on particular games (or other workloads) has never been measured.
For low-threaded workloads that always fit into L3, maybe.Small core complexes are an enabler of low latency of the L3 caches.
Precisely why AMD has the Epyc 4XXX line of glorified desktop processors for low end servers and workstations. A 2 CCD X3D parts would fit perfectly in that line and be priced accordingly.Ryzen is the consumer line, people use it for gaming and other compute tasks. The point is they are all consumer tasks. Really you get the single core CCD with vcache of you game, and if you want it for dual use as a workhorse you get the single CCD vcache.
If you really want to use the applications that benefit from vcache and large amounts of cores the last part of your paragraph is the important one. The product already exists and it's not for consumer. To provide it to consumer would mean lopping off lots of commercial income. The clamour for expensive hardware for cheap is, pointless. It's not a segment AMD will provide for you. It would be mad for them to do so...
Not bad. The iGPU performs a bit better than I expected, but digging into the benches, a lot of the performance gain on KRK is influenced by the higher 1t performance of Zen5 more than held back by the fewer CUs. In stuff that is less 1t dependent, it doesn't beat HPT. But the two solutions are very close.
For low-threaded workloads that always fit into L3, maybe.
But for a lot of workloads, a few cycles less L3 latency pale in comparison to having twice as much L3 to work with before having to go off-CCD/CCX, both in terms of power and latency.
AMD wouldn't be increasing core count + L3 per CCX/CCD for no good reason.
Why does the gen make a difference? AMD sells threadripper and EPYC vcache models. For some reason you've added that they need to be zen 5 for some reason?Not true - there is no 3D version of Turin and official message is that they won't do it this gen, so no - you can't get Zen 5 with both chiplets having 3D cache at all, for any money.
AMD said that they won't come this gen.
Well, I have the 9950X3D now so a dual V-cache CCD chip is landing any day now.so no - you can't get Zen 5 with both chiplets having 3D cache at all, for any money.
Not bad. The iGPU performs a bit better than I expected, but digging into the benches, a lot of the performance gain on KRK is influenced by the higher 1t performance of Zen5 more than held back by the fewer CUs. In stuff that is less 1t dependent, it doesn't beat HPT. But the two solutions are very close.
HPT still offers lots of PCIe lanes for a dGPU though, and anything with a 3050 or better will be miles better in gaming.
The cases where a 9700X is faster than a regular 9950X (running same clocks), is a few outlier games, so I really don't think dual CCD creates many problems in it self. With heterogeneous cores the differences will be larger, but again it seems like it is fixed in most games.I don't think that's true.
It's just hard to test, because most games are designed around 6-8 cores being mainstream and don't heavily utilise more cores to begin with.
AMD making games run only on the VCache-CCD of the x9x0X3D models doesn't help the difficulty of measuring it, but it's a strong indication that AMD's own testing suggested that cross-CCD latency hurts more than limiting games to 8C max, which is kind of telling.
There have been other indications in the past, like Matisse vs. Vermeer and Rembrandt.
A 5700X is up to ~60% faster than a 3700X in some games, even though the IPC in most non-gaming tasks is only 11% higher and clocks aren't that much higher, either.
Meanwhile, the 5700G with only half as much L3 (but same amount of maximum L3 available to 1 core as Matisse, if not all cores are fully utilised) craters down to being only about 20% faster in those games than a 3700X, but still beating the 11% IPC uplift we see in many other workloads.
That means up to 2/3 of the Zen3 performance uplift in games is coming from the doubled L3 size per core vs. Zen2, but a few more percentage points may be coming from avoiding cross-CCD latency.
For low-threaded workloads that always fit into L3, maybe.
But for a lot of workloads, a few cycles less L3 latency pale in comparison to having twice as much L3 to work with before having to go off-CCD/CCX, both in terms of power and latency.
AMD wouldn't be increasing core count + L3 per CCX/CCD for no good reason.
Higher clocks, full AVX512, better general IPC, 2st gen of DDR5 support, 12 mem channels, current product that will sell for a while?Why does the gen make a difference? AMD sells threadripper and EPYC vcache models. For some reason you've added that they need to be zen 5 for some reason?
Yeah sure, zen 5 would make those current products faster but if you want massive multi thread or vcache models of massive multi thread, those products exist today. AMD has a product to sell and they win those segments already. Would they be faster with zen 5, sure. But right now AMD has products on those segments, just they are too expensive for the minute number of hobbyists that want them but want to pay cheap prices that would make no sense for AMD to charge, considering what consumers with real workloads would buy them for.Higher clocks, full AVX512, better general IPC, 2st gen of DDR5 support, 12 mem channels, current product that will sell for a while?
They existed 3 years ago too in form of Milan-X, but why should I be buying that in 2025?if you want massive multi thread or vcache models of massive multi thread, those products exist today
Indications... As I said, we have no measurements yet. What's been measured so far doesn't isolate cache segmentation effects from cache segment size effects.There have been other indications in the past,
Conversely, AMD started the Zen line with 4-core CCXs for good reasons. (And slowly worked their way up from there.)AMD wouldn't be increasing core count + L3 per CCX/CCD for no good reason.
The (according to adroc) fork into separate desktop and server physical CCD variants surely doesn't help, as the production volume wouldn't be shared. There is also Azure's adoption of MI300C ( = HBM'ed EPYC) which I have seen painted as the reason against Turin-X. Zen 5 Threadripper alias Shimada Peak is still a wildcard though.there is no 3D version of Turin and official message is that they won't do it this gen,
Why should you be buying it? Because if you want high core count and high cache, it's got tons of performance.They existed 3 years ago too in form of Milan-X, but why should I be buying that in 2025?
-X model frequencies were pretty low, where as Zen 5 EPYC pushed them up very aggressively and since 3D cache is now at the bottom that means it could retain a lot of that frequency in -X model too, therefore making it FAR more superior than old stuff.
And why should AMD push people to old product when they need to sell new stuff? What's there to argue about - doing dual chiplet desktop is trivial, call it EPYC 4004 3D and sell for $999
no.I would be concerned that a full EPYC 3D cache version of Zen5 Turin would run into power and thermal problems.
It's just clocks.Yes, it's partly due to the cores running at higher clocks, but it's partly because there are more transistors and higher IPC on the same node as before.
Zen 5 consumer dies are a lot leakier I think than Zen 4 dies. That could explain the higher power usage.Yes, it's partly due to the cores running at higher clocks, but it's partly because there are more transistors and higher IPC on the same node as before.
They existed 3 years ago too in form of Milan-X, but why should I be buying that in 2025?
Maybe saving the V-cache dies for Venice-X, in case they think they could release them earlier than their own expectations. Also, since the Genoa-X CPUs are so expensive and there can't be that many customers with the specific need of really high cache who have no issue absorbing the additional cost as cost of doing business, it makes sense that AMD is not interested in flooding the market with more X server parts. The V-cache dies could also be getting more use in their Instinct accelerators that are in high demand.AMD may skip the -X on Turin...
Maybe saving the V-cache dies for Venice-X, in case they think they could release them earlier than their own expectations. Also, since the Genoa-X CPUs are so expensive and there can't be that many customers with the specific need of really high cache who have no issue absorbing the additional cost as cost of doing business, it makes sense that AMD is not interested in flooding the market with more X server parts. The V-cache dies could also be getting more use in their Instinct accelerators that are in high demand.
Yeah, no kidding, but that's not exactly where I was going with that post. Server CPUs, especially for providers with dense racks, are quite sensitive to power draw and thermal dissipation. I was speculating specifically that a TurinX3d part would have to take a significant clock hit to stay within the socket and chassis power and thermal limits to the point that the performance improvement over regular Turin parts wasn't sufficient to justify the price that AMD would have to ask in enough cases to make the business case for it's existence.no.
It's just clocks.
Same clocks as non-V$ parts means workload power is also the same.
d'oh.
dawg the power is defined at platform level.Server CPUs, especially for providers with dense racks, are quite sensitive to power draw and thermal dissipation
no it would clock like Turin.I was speculating specifically that a TurinX3d part would have to take a significant clock hit to stay within the socket and chassis power and thermal limits to the point that the performance improvement over regular Turin parts wasn't sufficient to justify the price that AMD would have to ask in enough cases to make the business case for it's existence.