Active power is helluva lot more things than that.
Bandwidth.
SP7 ain't a 16ch socket for kicks. It really needs all that and then some.
Active power is helluva lot more things than that.So leaking more DOESN'T make it consume more power?
Bandwidth.If so, then what IS the biggest one?
AFAIK the max frequency of a process can be increased by increasing gate pitch, which moves the transistors farther apart, which in turn creates a lower current density. This allows for higher leakage transistors, which allows for higher max frequency and power. Nothing is free so you need more die area and idle power is higher as well as the increased power for the "new" max frequency. I read this in Anandtech a long time ago.
Exactly to both of you.Yup that’s always been the trade-off between speed and efficiency. In very basic terms, the closer transisters are together, the shorter wires can be. The less distance power has to travel, the less you lose to things like voltage drop-off. That’s why denser transistors = better power efficiency. But if you want speed, you have to spread them back out some which costs power.
I think I am done playing with the slippery watermelon seed on the wet table top. When you decide to have a serious conversation about the trade offs between design considerations vs moving the goal posts around in order to justify an incorrect assertion (ie clock speed is all that matters argument), let me know.Active power is helluva lot more things than that.
Bandwidth.
SP7 ain't a 16ch socket for kicks. It really needs all that and then some.
I think you and adroc are somewhat talking past each other here:Ok, good. so you agree that tuning for max frequency makes the design use more power.
I'm no expert, but it's pretty obvious to me that at least for multi-threaded workloads, they're not.Would you agree that DC processors are highly power/thermal limited?
Do we know how many different ccd configuration are in play at this moment ?Btw this thread has already reached 100 pages and the launch of Zen 6 is still more than a year away.
Since Turin high core count variants seem to clock around the 3-4Ghz range, it appears that the assumption that "only transistor clock speed matters" is incorrect. My thought is that these parts are EITHER power limited by the socket, or thermally limited. Regardless of which it is, it ISN'T clock speed limited.I'm no expert, but it's pretty obvious to me that at least for multi-threaded workloads, they're not.
They're rather area-limited for example, because power/thermals can be kept in check by going wider (more cores, lower clocks/voltages), but only if the process density improvements allow for it, so I'd say that's a bigger bottleneck, especially when it comes to SRAM/cache.
Physical limitations with all those memory channels and PCIe lanes coming off the IOD are probably increasingly becoming a problem, too.
Not that I am aware of, but these are fantastic areas for discussion.Do we know how many different ccd configuration are in play at this moment ?
Do desktop & mobile ahare ccds or are they different?
I get the feeling that desktop will have a single ccx 12p ccd whereas mobile would have a dual ccx 4p 8c ccdsWithin desktop and laptop, we know there will be a 12c CCD, but we don't know if there will be lesser core CCD's. In theory, AMD could use the same 12c CCD and bin them into CCD's that pass with:
Now if you include a 2nd CCD within a processor you get a silly number of possibilities.
- 2 functioning cores
- 4 functioning cores
- 6 functioning cores
- 8 functioning cores
- 10 functioning cores
- 12 functioning cores
Since there is little room in the market for so much variation, I suspect it will be artificially limited to a fixed set of marketing numbers.
imo, a different CCD with less cores doesn't make sense. A 6 core CCD would reduce area by less than half, and you still have the full IO die and the same packaging. If the 12 core SKU costs $100 and the 6 core costs $75, I don't think it's worth it. 6 core desktop CPUs are going to be budget and niche in 2026. Zen5 can be repurposed for the bottom end of the stack.Not that I am aware of, but these are fantastic areas for discussion.
It seems very likely that the DC CCD's will be different than the desktop and laptop CCD's.
For HPC (Thread Ripper) I suspect it can share the DC CCD's.
Within desktop and laptop, we know there will be a 12c CCD, but we don't know if there will be lesser core CCD's. In theory, AMD could use the same 12c CCD and bin them into CCD's that pass with:
Now if you include a 2nd CCD within a processor you get a silly number of possibilities.
- 2 functioning cores
- 4 functioning cores
- 6 functioning cores
- 8 functioning cores
- 10 functioning cores
- 12 functioning cores
Since there is little room in the market for so much variation, I suspect it will be artificially limited to a fixed set of marketing numbers.
imo, a different CCD with less cores doesn't make sense. A 6 core CCD would reduce area by less than half, and you still have the full IO die and the same packaging. If the 12 core SKU costs $100 and the 6 core costs $75, I don't think it's worth it. 6 core desktop CPUs are going to be budget and niche in 2026. Zen5 can be repurposed for the bottom end of the stack.
Here's how I imagine the lineup will look.
All chiplet consumer parts would use the same CCD.
- desktop io die that uses regular DDR
- 24 core and 20 core R9
- 12 core R7
- 8 or 10 core R5
- premium mobile io die that's basically the sucessor to Strix Point. One CCD link. LPDDR support, bigger iGPU, an SLC, and maybe LP cores.
- 12 core R9
- 10 core R7
- mainstream/budget monolithic chip with 8 cores (6 of which are dense). LPDDR support, moderate sized iGPU
- 8 core R5
Their maximum boost clock speed seems to be a switching speed limit. Cf. Zen 5 speculation thread for why it's not 5.7 GHz like with Ryzens but 5.0 GHz or less. However, in well threaded loads, they operate of course at way less than max_f, and that's because of power usage. T_junction,max seems to be configured to 100 °C (I briefly searched and found only a 3rd party source for this) which does not look like a relevant limit to me if cooler/chassis/environment are properly done.Since Turin high core count variants seem to clock around the 3-4Ghz range, it appears that the assumption that "only transistor clock speed matters" is incorrect. My thought is that these parts are EITHER power limited by the socket, or thermally limited. Regardless of which it is, it ISN'T clock speed limited.
Agree.Their maximum boost clock speed seems to be a switching speed limit. Cf. Zen 5 speculation thread for why it's not 5.7 GHz like with Ryzens but 5.0 GHz or less. However, in well threaded loads, they operate of course at way less than max_f, and that's because of power usage. T_junction,max seems to be configured to 100 °C (I briefly searched and found only a 3rd party source for this) which does not look like a relevant limit to me if cooler/chassis/environment are properly done.
Edit: As for Zen 6/ Venice, my expectation is that they will keep it similar as with Zen 5/ Turin, the latter having either a 5.0 GHz 8c CCD or a denser 3.7 GHz 16c CCD. The only question to me is if there will be just 2 or even 3 CCD types for Venice — not just because of different clock speed vs. density targets but perhaps also because of packaging variants. Edit 2, I also expect that Venice won't regress vs. Turin WRT max_f; they might rather bump it up further in at least the per-core performance optimized SKUs.
Seeing how these threads grow exponentionally as we approach the release date and then die suddenly after launch I have a feeling it's going grow a lot over the next year!Btw this thread has already reached 100 pages and the launch of Zen 6 is still more than a year away.
Still got nothing on the previous one. I find it 32% more boring.Btw this thread has already reached 100 pages and the launch of Zen 6 is still more than a year away.
Congrats. Very efficient way to diss every poster in this thread in only 12 words and 1 number.Still got nothing on the previous one. I find it 32% more boring.
Wow. So leaking more DOESN'T make it consume more power?
And that didn't last long, A14 is just a new GAA node.Still TSMC A-next will probably be a clean sheet forksheet node and not N3+++ like A16.
yeah AMD have to settle for N2P if they want to launch in 2026I don't see N2X on TSMC roadmap for 2026.
Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/355121-tsmc-2025-technical-symposium-briefing/
I think neither one.So you are saying that you don't think the 3.7Ghz on the 16c CCD is thermally limited, but rather socket power limited?
That is just a poorly designed image. I wouldn’t read too much into it. I also wouldn’t assume Zen 6 is launching next year without official confirmation.I don't see N2X on TSMC roadmap for 2026.
Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/355121-tsmc-2025-technical-symposium-briefing/