Why not make them all X3D?
Costs of integration that is good enough for $400 retail product should be far more affordable than doing 48 MB SRAM on N2, plus a chance to increase L1/L2
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Why not make them all X3D?That would mean VERY different CCD designs for X3D vs non-X3D-- not going to happen.
Price x production complexity x lower yieldsWhy not make them all X3D?
Costs of integration that is good enough for $400 retail product should be far more affordable than doing 48 MB SRAM on N2, plus a chance to increase L1/L2
How do you explain high volume of 9800X3Ds sold for peanuts compared to server versions on per core basis? Clearly yields are good enough.Price x production complexity x lower yields
RDNA 5 WONT be late 2025 lol.
rdna 5 would be q1 27 if we account for the 2 year cadence
In addition to what others have said there's also the factor of not being able to price it at premium when it becomes a common part.Why not make them all X3D?
They all become super duper premium parts - N2 + larger L1/L2 + 3D cache = $$$it becomes a common part.
Because SP7 is larger?Wait a sec how are they going to cram 32 Zen 6 C core without increasing the area cause N3E to N2 is 15% and I can easily bet the core area is going to increase by a lot more than this.
They have a new socket .than it makes senseBecause SP7 is larger?
Easier to design.Why would they go to 32 cores when they could just put more dies?
You want less NUCA domains, not more.Why would they go to 32 cores when they could just put more dies?
Not enough SoIC wafer starts in the world for that.Why not make them all X3D?
Not really you just want the least amount of NUCA domains possible, especially for cloud parts.Easier to design.
Because adding the stacked L3 takes time... Obviously. Like, let's say the chiplet without the stacking can be made at time A, and stacking the L3 takes extra manufacturing steps, the time for that let's say is X. Since we all agree X is non 0, and it's not a few weeks, then they would have to artificially delay the launch of the non x3D chips to launch X3D at the same time. Why do that? X3D will always come later.Whatever they use for 3D versions - just move whole L3 cache to the bottom, that should free up space in chiplet.
Why much later? Took them a few months to launch 9800X3D and zero reason they could not have done it at launch as it should have been.
My guess is that servers is #1 goal for them, hyperscalers will certainly be getting them way ahead of launch
I don't think this is happening, but why does what you're saying have to be the case? We've heard that 2hi stacks is a possibility here. What if one stack is standard and 2 stacks is the addition of extra cache?That would mean VERY different CCD designs for X3D vs non-X3D-- not going to happen.
Theoretical Zen 6 EPYC CCD on N2.What 32c/64t part are you talking about? What in this thread, or from elsewhere, makes you think that exists?
Sperate question ...N2 is relatively expensive, what part from desktop, server and laptop would you want to come out first?
Zen 5c Turin was 84.5mm2 on N3E. I expect that N2 would be ~20% more dense than N3E. So double the cores -> 169 and take off 20% -> 135mm2. So you are right. Quite a bit smaller than 200mm2. Even if more logic is added to Zen 6, it would likely weigh in around 150mm2 ish.He means the 32c server chiplet with Zen 6 Dense. But I think that should be much smaller than 200mm2.
See above. I used 20%, but the numbers would still be close.Wait a sec how are they going to cram 32 Zen 6 C core without increasing the area cause N3E to N2 is 15% and I can easily bet the core area is going to increase by a lot more than this.
Agree.The 16C Zen 5 Chiplet in N3E is ~82mm2 big. Now you get N2 and a smaller PHY for the interconnect to the IOD. So it could be very well the case, that we land at ~150mm2 or so for 32C. Maybe even less.
Yes. I am guessing quite a bit bigger as they are looking to put so many DDR channels on it. Additionally, I hear the socket power limit is being raised quite a bit as well.But wasn't speculated, that Zen 6 gets a new socket with 16ch DDR and therefore a bigger socket as well?
Agree.That would mean VERY different CCD designs for X3D vs non-X3D-- not going to happen.
That's really not what it is man.So double the cores -> 169 and take off 20% -> 135mm2. So you are right. Quite a bit smaller than 200mm2. Even if more logic is added to Zen 6, it would likely weigh in around 150mm2 ish.
So what is it then because obviously you know so why hold back on us?That's really not what it is man.
You're so close man. So damn close.It only makes sense that it's eventually coming where they start designing certain CCDs with no L3 at all. I wouldn't be at all shocked if Zen7 CCDs had larger L1 and L2 with no L3 at all and all of them were produced with a healthy slab of stacked L3 for DC applications. Consumer might get a half implementation of things with smaller L2, the mobile 2MB of L3 per core and have the option of having stacked L3. Lower SKUs could be stuff like 6 and 8 core chips with full L3 but no stacked and higher SKUs could be things like 10, 12, or even 16 if they get larger, but all with the stacked cache.
This just sounds like cope.You're so close man. So damn close.
They can announce it during launch to be available in X months, how about that? And start pre-orders immediately. Then people have certainty.X3D will always come later.
Or sarcasm. AT has no idea what Zen 7 is going to be.This just sounds like cope.
Or sarcasm. AT has no idea what Zen 7 is going to be.