Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

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DisEnchantment

Golden Member
Mar 3, 2017
1,774
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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.




Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE
 
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511

Golden Member
Jul 12, 2024
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I wouldn’t say tiny, but smaller. There’s been some promising research in this area that might let them keep it bigger.
Are you referring to Directed Self Assembly to stich dies?
High NA is the point where the max die size will be tiny, right?
It reduces the die size from 26*33(858mm2) to 26*16.5 (429mm2) still enough for most things.
 

mpumalanga

Junior Member
Feb 18, 2022
17
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That slide has "Best Wafers" at the lower left.

Do they mean only the best wafers have that HVM (DO)? If yes, then what is the # for the average wafer?

In short, is this some BS/misdirection?
No units in that graph on the y axis and introducing on new term "Best Wafers" with no definition of what it means.
Intel tries to hide something.
 

DavidC1

Golden Member
Dec 29, 2023
1,449
2,356
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14A vs 18A 15-20% perf/watt and 1.3 Density so Intel will lag TSMC with A14 by 10% but will be 1 yearly if they don't mess up.

View attachment 122901

I said TSMC will have 10% density advantage in A16 vs 14A comparisons with Intel claiming 20% density over 18A. Now they are saying 30%.

So compared with 14A, TSMC's A14 seems to be just 5-6% more density. Compared to TSMC's A16, Intel's 14A is now 3-4% more dense.

Intel will have speed advantage in both cases. The differences between them are very small though either way.
 

jdubs03

Golden Member
Oct 1, 2013
1,232
871
136
That slide has "Best Wafers" at the lower left.

Do they mean only the best wafers have that HVM (DO)? If yes, then what is the # for the average wafer?

In short, is this some BS/misdirection?
Obviously based on that graph the answer to your question is not feasible to answer.
But from the looks of that defect density plot; they're about a year away from having their average wafers being at the level of the best wafers today.
 

511

Golden Member
Jul 12, 2024
1,896
1,705
106
That slide has "Best Wafers" at the lower left.

Do they mean only the best wafers have that HVM (DO)? If yes, then what is the # for the average wafer?

In short, is this some BS/misdirection?
Best wafers can be the best wafer they have matches the DD of HVM while average is lot less
 
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