Wrong. https://www.techpowerup.com/335752/...mory-at-ddr5-6000-cl32-overclocked-speed?cp=1 as I said 64GB/stick is available. It might be crazy expensive but it is there.ECC UDIMMs still top out at 48 GB/stick.
In Epyc or if you stick to AMD spec, as the Gskill kit from the link above is rated at 6000MT/s, and has been shown to overclock above that. Yes, the secondary timings are worse than in smaller kits but the BW stays.Bandwidth is reduced at 2 DIMMs per channel.
Falcon Northwest will happily sell you the base config for $8000...I wonder how much a 16 to 24 core TR would go for, and then the motherboard...and RAM xD
Only matter of time - the fact that 64 GB DIMMs appear in consumer space is very encouraging!Indeed, my bad.
I would rather prefer they introduce a new dual socket chipset for the consumer Ryzen. Wouldn't mind paying $1000 for such a mobo and they get to sell twice the CPUs!I am hoping they juice the clocks, for non-Pro variants, at least. Give me the same peak clocks I get on Ryzen!
I understand wishful thinking but this is like the worst thing they could do with dual socket.I would rather prefer they introduce a new dual socket chipset for the consumer Ryzen. Wouldn't mind paying $1000 for such a mobo and they get to sell twice the CPUs!
Tri-channel RAM would be a bonus (I know they wouldn't be OK going up to quad channel because they would hate to piss off existing TR users).
At least with dual socket, you can have TWO CPUs, each with tri-channel RAM which should help LLMs.I understand wishful thinking but this is like the worst thing they could do with dual socket.
Sure, for token generation this should do fine. But for eveything else numa aware software would be preffered and that is sometimes hard to come by in consumer targeted software.At least with dual socket, you can have TWO CPUs, each with tri-channel RAM which should help LLMs.
A compromise is to spread the software threads across both sockets using Process Lasso. I tried on my 128 thread Epyc and it was able to run my non-NUMA aware workload (my rudi benchmark actually) across both NUMA domains using 32 threads from each domain (the limit in Windows is 64 threads max unless you use some trickery). I think it would work the same on a dual socket system if it's defined as two NUMA domains.But for eveything else numa aware software would be preffered and that is sometimes hard to come by in consumer targeted software.
This trickery is called reading documentation https://learn.microsoft.com/en-us/windows/win32/procthread/processor-groupsthe limit in Windows is 64 threads max unless you use some trickery
And yet people buy these so somebody might need them, hmm (no I don't know the volume but since Gigabyte and Asus bother with the mobos then they at least break even)A southbridge on board… which nobody needs when there are plenty of PCIe slots.
At this point you have made the physical package big enough to fit 2 additional CCDs, since the core count is matched you can free the intersocket links as the second socket is no longer needed so you get more usable PCIe links. Hmm, sounds like a ThreadripperUpgrade all the PCIe lanes to 6.0
Make the two x4 links for the SSDs the processor to processor x8 PCIe 6.0 coherency link. (64GB/sec, more than a quadrant like on Epyc Rome)
X4 6.0 to the I/O chipset, two of them for dual x970, 48 PCIe 5.0 lanes, +40 other usable lanes.
The author of Rapydmark is a much more accomplished developer than I could ever be and he didn't implement this so it's bothersome enough to be called trickery.This trickery is called reading documentation https://learn.microsoft.com/en-us/windows/win32/procthread/processor-groups
Ah I did not spot the 6.0 -> 5.0 thing. Still, this will be usable but carry some BW limitation which might not be ok for some use cases, but might be fine for others.Um, no. It's the same physical package for both processors. The only major change is the additional mode for the PCIe links coming out of the I/O chiplets (already demonstrated know how from Epyc).
This could be done on package too, I am not sure where cost balance would be better, but the ease of use would favour single socket solution.What would be REALLY cool is if you could use an X3D processor in the first socket and a normal one in the second. For Zen5, that could look like one 12 core X3D CCD and one normal CCD in the first package, and two 12 core normal CCDs in the second. 48 cores, 4 channels, 12 with VCache.
There might be a lot of different reasons why this was not implemented, so I would not assume it to be some sort of trickery. Unless you heard that from the dev himself.The author of Rapydmark is a much more accomplished developer than I could ever be and he didn't implement this so it's bothersome enough to be called trickery.
What would be REALLY cool is if you could use an X3D processor in the first socket and a normal one in the second. For Zen5, that could look like one 12 core X3D CCD and one normal CCD in the first package, and two 12 core normal CCDs in the second. 48 cores, 4 channels, 12 with VCache.