Question Zen 6 Speculation Thread

OneEng2 · Friday at 8:23 AM

511 said:
N2 shrink only gets you 1.2 also N4P to N3E is 1.3 ish that is for same design and this doesn't take FinFlex into account

Turin D 16 core CCD is already on N3E. The shrink from N3E to N2 is 25%.

reaperrr3 said:
What?
A 75mm² N2 CCD that will be used all the way down to 250$ products is fine, but 8 ~170mm² CCDs for 10k+ server CPUs is somehow not viable from a business perspective?

The current Turin D CCD is ~85mm2. While it is possible for AMD to make a 170mm2 CCD, do you believe it is reasonable to expect them to?

reaperrr3 said:
Don't dismiss this 32c just because adroc is one of the people claiming it's real...
You make it sound like AMD doesn't have crazy good margins in their server CPUs already, and the CCD silicon is only a relatively small part of the cost anyway.

I'm also not convinced the 32c will be more than twice the size of the 12C.
The 32c CCD uses denser cores, possibly only 64MB L3, and won't have twice the IF connection stuff of the 12C CCD, either.

Fair point about adroc.

The 85mm2 Turin D CCD already takes into account that Zen 5c is smaller than full Zen 5 core. Shrinking from N3E to N2 gives you a 25% density improvement. 16 cores * 1.25 = 20 cores.

You are correct that my 170mm2 was off (again). 85/20 = X/32. X=136mm2.

This is certainly possible; however, the determination of if it is PROBABLE lies in if AMD will give up the profit to do it. While they COULD do it, it would be very expensive in comparison to the 20 core version.

The real question is will AMD NEED more than a 20c EPYC D to become the undisputed DC cloud computing option?

511 · Friday at 8:39 AM

OneEng2 said:
Turin D 16 core CCD is already on N3E. The shrink from N3E to N2 is 25%.

TSMC says otherwise also logic is 1.2X Chip Density is 1.15X.

OneEng2 said:
The current Turin D CCD is ~85mm2. While it is possible for AMD to make a 170mm2 CCD, do you believe it is reasonable to expect them to?

Fair point about adroc.

The 85mm2 Turin D CCD already takes into account that Zen 5c is smaller than full Zen 5 core. Shrinking from N3E to N2 gives you a 25% density improvement. 16 cores * 1.25 = 20 cores.

You are correct that my 170mm2 was off (again). 85/20 = X/32. X=136mm2.

This is certainly possible; however, the determination of if it is PROBABLE lies in if AMD will give up the profit to do it. While they COULD do it, it would be very expensive in comparison to the 20 core version.

The real question is will AMD NEED more than a 20c EPYC D to become the undisputed DC cloud computing option?

First thing regular Turin CPUs are way more popular than the D ones.

Win2012R2 · Friday at 9:29 AM

511 said:
First thing regular Turin CPUs are way more popular than the D ones.

Depends among whom, D target market is Meta.

511 · Friday at 9:32 AM

Win2012R2 said:
Depends among whom, D target market is Meta.

For general market ofc and OFC Meta and MSFT and Google is big on AMD these days only exception is Amazon who seems to favor Intel Amazon packs chips at Intel as well.

LightningZ71 · Friday at 10:19 AM

Is there a reason that Zen6 dense for DC products MUST include full width AVX-512? They could further reduce the core by using the slightly smaller half width AVX-512 implementation they did in Zen5 mobile. With that many cores, it may not make much of a difference given memory throughput constraints, even with that many channels. It's a whole separate CCD, they can make further core optimizations on it without affecting other products...

Win2012R2 · Friday at 10:31 AM

LightningZ71 said:
using the slightly smaller

If it's slightly smaller, then why risk big drop in perf for increasingly more software that supports it?

LightningZ71 · Friday at 10:34 AM

"slightly smaller" is relative, and gets amplified over 24/32 cores, depending on the layout. It can have a big impact on the final size of the CCD.

Joe NYC · Friday at 10:40 AM

adroc_thurston said:
what's a 4 IOD and how do I escape route 16 memory channels outta datboi.

It seems that Intel has a good idea to position the IO Dies on the sides of the CPU rather than in the middle. But disadvantage of that is that there may be a need for some sort of mesh in the base die.

AMD has, so far, had a single connection from CPU chiplets to IOD, While IO Die is responsible for - well IO.

The idea posted by MLID is that this continues, but there could be multiple IODs, and only the IODs are linked. For that, central positioning of IODs (rather than edge as intel has it) is better.

But that does not answer the question of how you connect to all the IO, if IO Dies are centrally located.

It seems that a good sized RDL / base wafer could do the job...

LightningZ71 · Friday at 11:13 AM

There could be a silicone interposer under the IO Dies that runs the length of the 4. It can be narrower than the IODs to allow the shoreline connection from the CCDs and have sub-surface connections out to the socket contact pad through the substrate.

adroc_thurston · Friday at 12:54 PM

Joe NYC said:
It seems that Intel has a good idea to position the IO Dies on the sides of the CPU rather than in the middle

How would that ughhh work.

Joe NYC said:
AMD has, so far, had a single connection from CPU chiplets to IOD, While IO Die is responsible for - well IO.

It's a Northbridge. It's responsible for literally everything.

Joe NYC said:
The idea posted by MLID is that this continues, but there could be multiple IODs, and only the IODs are linked. For that, central positioning of IODs (rather than edge as intel has it) is better.

They're just halves.
AMD does stupid simple designs and whatever overcomplication you're thinking of is just not real.

Joe NYC · Friday at 2:37 PM

adroc_thurston said:
How would that ughhh work.

Here is a picture. Intel's base provides connectivity, presumably in a mesh fashion.

adroc_thurston · Friday at 2:49 PM

Joe NYC said:
Here is a picture. Intel's base provides connectivity, presumably in a mesh fashion.

Well yeah it sucks.
AMD ain't doing that.
Intel ain't doing that for much longer either.

Joe NYC · Friday at 2:54 PM

LightningZ71 said:
There could be a silicone interposer under the IO Dies that runs the length of the 4. It can be narrower than the IODs to allow the shoreline connection from the CCDs and have sub-surface connections out to the socket contact pad through the substrate.

The way I understood MLID take on this that there would be a "module" with IOD and 2-4 CCDs. They could be connected using a (large) base wafer with RDL type connection.

Then these modules would connect to one another using a bridge of some kind. Presumably silicon bridge, possibly using hybrid bond for interconnect. (could be something else)

That was a leak from some time ago (year+) so who knows how related it is to reality. But given quickly we are approaching Venice release, AMD already has a solution in place, we just don't know what it is.

Joe NYC · Friday at 2:57 PM

adroc_thurston said:
Well yeah it sucks.
AMD ain't doing that.
Intel ain't doing that for much longer either.

Interestingly, Intel added another level of complexity in putting SRAM transistors on the base die (with Clearwater Forrest) - which is now experiencing some delays.

adroc_thurston · Friday at 4:17 PM

Joe NYC said:
Interestingly, Intel added another level of complexity in putting SRAM transistors on the base die (with Clearwater Forrest) - which is now experiencing some delays.

AMD did too, for MI300. But that's not how you build a modern CPU.

Joe NYC said:
we just don't know what it is.

yeah we do it's very very simple.

OneEng2 · Friday at 6:05 PM

511 said:
TSMC says otherwise also logic is 1.2X Chip Density is 1.15X.

Not sure where I got the 25%; however, if your link is accurate, then it becomes even more unlikely that AMD would produce a 32c Zen 6c CCD.

511 said:
First thing regular Turin CPUs are way more popular than the D ones.

Agree. I went with the assumption that both EPYC Zen 6 (full) and desktop chips would be sharing the 12c/24t CCD.

LightningZ71 said:
Is there a reason that Zen6 dense for DC products MUST include full width AVX-512

Taking out the 512bit data path is a pretty big tear up IMO. I am guessing it just isn't worth it.

adroc_thurston · Friday at 6:39 PM

OneEng2 said:
Not sure where I got the 25%; however, if your link is accurate, then it becomes even more unlikely that AMD would produce a 32c Zen 6c CCD.

Why would it even be unlikely or hard?

reaperrr3 · Friday at 7:57 PM

OneEng2 said:
The current Turin D CCD is ~85mm2. While it is possible for AMD to make a 170mm2 CCD, do you believe it is reasonable to expect them to?

Yes.

First of all, keep in mind Venice-D would very likely use only 8 CCDs, while regular Venice would use 12, same CCD ratios as the current Turins.
So with ~75mm² x 12 vs. ~140mm² x 8, we're only talking about ~25% more total CCD silicon area for 77.7% more cores.
If there's customers willing to pay anywhere from ~50-70% higher prices for these 77% more cores per socket, it'll be more than worth it.

Second, AMD can't know for sure when Intel starts doing good things again, or when some ARM server CPUs start to catch up in both per-core-perf and core count.
For customers who want as many decently-performing cores per socket as possible, AMD can't really move too fast on that front.
If they happen to end up way ahead of the competition, they can just price that into the higher SKUs + gain more market share.
I mean, TSMC is a prime example that being by far the best option for something is what makes you successful.
If the market is very competitive, you may be forced to sell products at modest margins.
If you're far ahead of the competition, you can demand a premium and customers will still pay.

Additionally, past a certain point there's diminishing returns for going with smaller CCDs and more IF links.
8x32c is likely more sensible overall than for example 16x16c, for example.

OneEng2 · Friday at 9:26 PM

reaperrr3 said:
So with ~75mm² x 12 vs. ~140mm² x 8, we're only talking about ~25% more total CCD silicon area for 77.7% more cores.

There is quite a huge difference in defect rate between 75mm2 and 140mm2, and we are talking about a very new process (and the most expensive process) as well.

I am not saying that AMD wont do it, I am speculating (as this is a speculation thread ) that they will not want to do it.

I am guessing it is more likely they will scale out with more IOD's.

Another reason to believe they will scale out with more IOD's is because for DC applications, they need the bandwidth per core to stay high. I am guessing they need 4 channels of memory to feed 80 cores (20 per CCD, 4 CCD per IOD)

reaperrr3 said:
Second, AMD can't know for sure when Intel starts doing good things again

Now THAT is the most compelling argument I can see.

If Diamond Rapids comes in only 128 P core, then I expect that AMD will not feel the need to have more than 144 (3 IOD) .... but I wouldn't count out a 4 IOD 192 core EPYC Zen 6.

As for EPYC Zen 6c Dense, it will likely be facing Clearwater forest with 288 cores. A 20 core CCD Zen 6c using 3 IOD's would be 240 cores .... but each of these cores will likely be equal to 1.4 "mont" cores due to SMT making a 240 core Zen 6c dense equivelent to a 336 core Clearwater forest .... more than a match for the Intel offering without the need to go to a 4 IOD monster.

I am thinking that in both cases, AMD maintains DC superiority by a good margin with:

EPYC Zen 6: 12c/24t CCD & 3 IOD's = 144 cores
EPYC Zen 6c Dense 20c/40t CCD & 3 IOD's = 240 cores

adroc_thurston · Friday at 9:30 PM

OneEng2 said:
EPYC Zen 6: 12c/24t CCD & 3 IOD's = 144 cores
EPYC Zen 6c Dense 20c/40t CCD & 3 IOD's = 240 cores

Venice-Dense is 256c in 32*8 layout.

Kepler_L2 · Friday at 11:11 PM

https://twitter.com/x/status/1921027706772181472

branch_suggestion · Friday at 11:21 PM

Kepler_L2 said:
https://twitter.com/x/status/1921027706772181472

So SP7 is 8CCD max or SP7 is dense only?
Also very nice to see 4MB L3/core on the dense die. Question is the topology, is it 2 16c CCXs or a unified 32c CCX which would likely require a more complex mesh?

Joe NYC · Friday at 11:30 PM

Kepler_L2 said:
https://twitter.com/x/status/1921027706772181472

Up to 128 MB of L3 per CCD would imply full 4 MB L3 per core in 32 core chiplet. Unlike the previous Dense chiplets that used only 2 MB of L3 per core.

adroc_thurston · Friday at 11:35 PM

Joe NYC said:
Up to 128 MB of L3 per CCD would imply full 4 MB L3 per core in 32 core chiplet. Unlike the previous Dense chiplets that used only 2 MB of L3 per core.

Bingo!

branch_suggestion said:
SP7 is dense only?

Indeed, classic SP7 did not survive (interrogation).

Kepler_L2 · Friday at 11:38 PM

branch_suggestion said:
Question is the topology, is it 2 16c CCXs or a unified 32c CCX which would likely require a more complex mesh?

Single CCX

Question Zen 6 Speculation Thread

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