Would be funny if it is just the classic Zen CCX layout but chungus.Single CCX
No 192 Cores Zen 6 🤔
Bingo!
Not to mention 16 Channel DDR5 with either 7200 or 8000 MT/sWow, that's unbelievable compute in a single CCD! And with 128MB L3 shared among all cores, A lot of bandwidth usage stays withing the CCD, putting less strain on memory controllers and memory itself.
The thing with silicon area and yield is it exponential so is the cost to make them.Yes.
First of all, keep in mind Venice-D would very likely use only 8 CCDs, while regular Venice would use 12, same CCD ratios as the current Turins.
So with ~75mm² x 12 vs. ~140mm² x 8, we're only talking about ~25% more total CCD silicon area for 77.7% more cores.
If there's customers willing to pay anywhere from ~50-70% higher prices for these 77% more cores per socket, it'll be more than worth it.
I bet AMD is expecting some moves from Intel if they don't they will end up in Intel's place and be surprised.Second, AMD can't know for sure when Intel starts doing good things again, or when some ARM server CPUs start to catch up in both per-core-perf and core count.
TSMC has been amazing in the last 10 years.For customers who want as many decently-performing cores per socket as possible, AMD can't really move too fast on that front.
If they happen to end up way ahead of the competition, they can just price that into the higher SKUs + gain more market share.
I mean, TSMC is a prime example that being by far the best option for something is what makes you successful.
If the market is very competitive, you may be forced to sell products at modest margins.
If you're far ahead of the competition, you can demand a premium and customers will still pay.
Well it's a mesh.Would be funny if it is just the classic Zen CCX layout but chungus.
Ehhhh N3b went tits up (sort of).TSMC has been amazing in the last 10 years.
They kinda got back on track with N2,Ehhhh N3b went tits up (sort of).
Yeah N3B was bad I almost feel bad for Intel cause the amount they prepaid for was ridiculous and it was disappointing imagine paying so much and still getting the same perf/watt as N4P 🤣.Well it's a mesh.
Ehhhh N3b went tits up (sort of).
It's actually a fair bit better but density was a huge miss vs projections.and still getting the same perf/watt as N4P
ask TSMC for this they are trying to create history by competing with Intel 14nm+++++.Why so many node variants? N3, N3B, N3E, N3P, N3X... 5+ node variants per node! don't they cost too much to create in the first place?
Well, there will most likely be 192c SKUs of Venice-D.No 192 Cores Zen 6 🤔
Well D SKUs gimp the per core performance die to drop in frequencyWell, there will most likely be 192c SKUs of Venice-D.
Since Venice-D removes the L3-per-core disadvantage of Turin-D, I doubt many customers will care.
A 192C with 12C CCDs would've been much more complex and expensive to make, while probably too power-constrained to perform much better than a 192c Venice-D (possibly even performing worse in some scenarios, because of less L3 per CCD).
The work will have already been done. Their mobile cores are exactly that going forward (or so say the rumors).Not sure where I got the 25%; however, if your link is accurate, then it becomes even more unlikely that AMD would produce a 32c Zen 6c CCD.
Agree. I went with the assumption that both EPYC Zen 6 (full) and desktop chips would be sharing the 12c/24t CCD.
Taking out the 512bit data path is a pretty big tear up IMO. I am guessing it just isn't worth it.
I find it HIGHLY unlikely that AMD is going to drop EPYC Zen 6 full core count down to 96 cores.
I am thinking this is a little too far off the side of reason as well.No 192 Cores Zen 6 🤔
Yeah, it will cost AMD 50 bucks extra but reduce NUMA nodes by half, discerning customers will pay a lot for that.I believe a 32c CCD is technically possible, but it may well be economically inferior. Think of it this way....
Maybe we're finally getting SMT4 😏I find it HIGHLY unlikely that AMD is going to drop EPYC Zen 6 full core count down to 96 cores.
Well, the market is ~20 million a year of which AMD has the majority of now IIRC. Lets say 10 million. (wild guess and based on chatgpt market numbers)Yeah, it will cost AMD 50 bucks extra but reduce NUMA nodes by half, discerning customers will pay a lot for that.
Hmmm, what is the reason for downgrading the Venice's core count back to the Genoa level? Are Zen 6-based EPYCs really going to be "F" only with the rest being based on Zen 6c?
With Zen6c now having the same amount of L3 as regular Zen6 the performance difference is probably not that big outside of lower core count higher frequency SKUs.Hmmm, what is the reason for downgrading the Venice's core count back to the Genoa level? Are Zen 6-based EPYCs really going to be "F" only with the rest being based on Zen 6c?
That would be the most sensible conclusion to me, especially assuming that N2 brings with it higher frequency it's possible the Dense Zen6 parts will be able to match all core frequency of Zen5 non-dense parts, and pull ahead thanks to other architectural changes.Hmmm, what is the reason for downgrading the Venice's core count back to the Genoa level? Are Zen 6-based EPYCs really going to be "F" only with the rest being based on Zen 6c?
It's an upgrade, SP6 parts top out at 64c.Hmmm, what is the reason for downgrading the Venice's core count back to the Genoa level?