That's the best argument I have heard so far.Developing Zen 5 for 2 nodes is like pain in the ass for AMD, not sure if they'd like to do it again.
It was a homage to the trend here lately of posting info and claiming that it's correct for certain, and then not providing anything to back that up. Hence the " " also included in the post.Which presentation slides?
You're not saving anything.Still, if you look at the billions they would save on a less expensive node
You're not saving anything.
N2 is like 10-15% more expensive than N3p.Besides the 40%+ cheaper wafer costs?
N2 is like 10-15% more expensive than N3p.
That's what it is, yeah.Uh, yeah...
Well yeah N2 isn't HVM yet.and N3P yields are better than N2 as of rn.
Some.go on the recently mentioned N3C node,
N3e/p/c are the same thing with the same maturity™, just with more options™.or are they going to push for a matured N3E or just push for a long term part on the N3P?
They aren't.The savings are bigger with N4P and while you make bigger sacrifices in area and clock/power that's perfect for lower end parts
Isn't that just DTCO you're describing?Contrary to what other posts have stated, AMD and TSMC have worked closely on optimized libraries for developing high frequency, high performance CPUs since/before Zen 3 (i.e. a custom process).
Hard to say if this is the right thread to continue, but...In this video hardware unboxed seems to hint about new AM5 cpu coming in Q3, multiple times infact
Any ideas what could be incoming ?
Strix Halo on AM5 ?
Fire Range SKU's ?
Dual X3D CCD "9960X3D" ?
View attachment 124370
Could this be where Kepler's earlier rumour about Zen 6 needing new ram came from? I think he speculated on it being LPCAMM2 ram and therefore needing a 2027 release date. Or maybe its Zen 6 mobile that needs LPCAMM2... which could fit a 2027 release window if desktop is released in h2 2026?Hard to say if this is the right thread to continue, but...
Computerbase reports that mainboard makers told them at Computex that CUDIMM support is coming, presumably with a new cIOD. Which datarates will be supported then is not yet fixed.
Nobody said, that, though?Fair enough; however, believing that N2 would be used for ALL Zen 6 markets flies in the face of history and common sense.
N3 was a completely new process vs. N5/4.N2 will ALSO be limited in supply, expensive, and lower yield than N3.
Multiple people with access to official internal AMD slides have clearly stated thatBest speculation I have seen in this thread for some time .
I tend to disagree though. I think it more likely that we will see:
Zen 6 10950X
12c CCD x2 = 24 (full Zen 6) + 4 LP Zen 6c on IOD
N3P
2026 Q2
$699
N2 GAA is a pretty big change from N3E. I believe that your assumption that isn't comes only from the fact that the same class of lithography machine is used to create both. I believe that the changes are so significant between N3E and N2 that we will surely see a loss of yield for quite some time .... if not indefinitely .... over N3E simply due to the larger number of steps in the process.N2 is mostly just GAA transistors on the N3E/P BEOL, so if they got GAA transistors under control, there's no reason for a significantly lower yield or significantly higher prices.
N2 ~ 30K/waferi heard it's 11% more expensive than N2 which matches your figure but the advantage for N3P is fabrication time it is faster to churn out N3P wafer than it is to N2 wafer and N3P yields are better than N2 as of rn.
N2 GAA is a pretty big change from N3E. I believe that your assumption that isn't comes only from the fact that the same class of lithography machine is used to create both. I believe that the changes are so significant between N3E and N2 that we will surely see a loss of yield for quite some time .... if not indefinitely .... over N3E simply due to the larger number of steps in the process.
The process time will most certainly be longer per wafer.
N2 ~ 30K/wafer
N3E ~20K/wafer
Quite a bit more expensive than 10%. Do you have information that suggest otherwise? There was copious amounts of media on the 30K/wafer pricing when it came out, and N3E is well documented. My assumption is that N3P will be about the same as N3E.
It is basically N3P design rules but GAA, remember that N16 was basically N20 but FinFET.N2 GAA is a pretty big change from N3E.
Yes but at that time N16 was not so complex compared to N20 if you compare N3E to N2.It is basically N3P design rules but GAA, remember that N16 was basically N20 but FinFET.
Same deal here, and A16 is N2P with BSPDN.
A14 is completely new, N2 family is heavily N3 derived.
Back in late 2018, Vega 20 was the first chip to come out along with a couple of phone socs on N7, which was as big of a jump as N2 is supposed to be. I don't understand why some people keep repeating the same old talking points, that N2 is too expensive bla bla, as if they actually know any hard data point.It is basically N3P design rules but GAA, remember that N16 was basically N20 but FinFET.
Same deal here, and A16 is N2P with BSPDN.
A14 is completely new, N2 family is heavily N3 derived.
They did this so its the opposite of a pain for them. Instead of having one big engineering team only focus on one node, they can get experience and time on advanced nodes that will wind up being bog standard in a year or two. Also they have a customer base for the dense dies, and fabbing them on a bigger process where they'd get lower yields only makes sense if like they had some urgency to it.Developing Zen 5 for 2 nodes is like pain in the ass for AMD, not sure if they'd like to do it again.