Discussion [Speculation] Working silicon that must exist because I don't see why it wouldn't

igor_kavinski · May 27, 2025

This post got me thinking: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...ranite-ridge-ryzen-9000.2607350/post-41453341

These are things I believe actually exist, somewhere, in the world:

Strix Halo running with desktop DIMMs

Tejas 7 GHz booting Windows 11

6 GHz ARM CPU that can emulate an x86-64 CPU almost perfectly

An Intel CPU that pretends and fools everything into believing it's a Ryzen and vice versa

AM5 mobo with DDR4 slots

AM4 chipset mobo with Zen 5 CPU in an AM4 package

10 core Lion Cove CPU with AVX-512 and quad channel RAM

295K that can run at least one core at 6 GHz but it cannot sustain that speed for more than a few seconds

Zen 5 CPU with enhanced IOD that runs EXPO CUDIMM DDR5-10500

8C/16T Ice Lake mobile chip with eDRAM

Did I miss something?

zir_blazer · May 27, 2025

igor_kavinski said:
AM5 mobo with DDR4 slots

AM4 chipset mobo with Zen 5 CPU in an AM4 package

Second one I recall that I mentioned multiple times as a possible Plan B for AMD if DDR5 failed to come down in price and killed the platform appeal, cause they should be able to interface Zen 4 CCD with a previous AM4 IOD - is literally what the whole Chiplet thing was about. First one doesn't make sense precisely because that, nothing pointed out that they intended to have hybrid DDR support on same Socket.

igor_kavinski said:
An Intel CPU that pretends and fools everything into believing it's a Ryzen and vice versa

Something like this was done in the past with a VIA CPU that uncovered that Intel was cheating on benchmarks. You may also achieve similar results via virtualization to catch CPUID and return whatever you want.

You're missing AMD Kaveri with soldered GDDR5, which was rumored at some point.
Raptor Lake-S with AVX-512 enabled.

Fun things we have actually seen:
A single working Intel Timna (Pentium 3 era SoC with integrated Memory Controller and GPU but no Cache)
Working Haswell-E/Broadwell-E with DDR3
Pentium 4 Prescott with EM64T enabled for Socket 478

CPU World / CPU Shack usually has some interesing histories about very niche parts and prototypes, but I can't remember any in particular.

igor_kavinski · May 27, 2025

zir_blazer said:
First one doesn't make sense precisely because that, nothing pointed out that they intended to have hybrid DDR support on same Socket.

It may exist if AMD made sure that they had a proper answer to a possible P-core only 10-core Alder Lake with IMC as strong as 10900K and could work at XMP DDR4-4400 easily. That would surely have put them in a really bad situation with Ryzen only able to leverage DDR5-4800 and its worse latency. Later benchmarks showed that Alder Lake needed at least DDR5-7000 to beat DDR4-4000.

NTMBK · May 29, 2025

You forgot Kaveri with a quad-channel memory controller and a big boi GPU. I refuse to believe that AMD didn't consider this back when they were designing the APUs for the PS4 and XBox One.

alcoholbob · May 29, 2025

Since Silicon Lottery is gone (the website), I wonder if there exists a unicorn 9950X3D, or 14900KS or 285K that can run stock all-core clocks at some absurdly low voltage, like 1.1V.

Thunder 57 · May 29, 2025

igor_kavinski said:
This post got me thinking: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...ranite-ridge-ryzen-9000.2607350/post-41453341

These are things I believe actually exist, somewhere, in the world:

Strix Halo running with desktop DIMMs

Tejas 7 GHz booting Windows 11

6 GHz ARM CPU that can emulate an x86-64 CPU almost perfectly

An Intel CPU that pretends and fools everything into believing it's a Ryzen and vice versa

AM5 mobo with DDR4 slots

AM4 chipset mobo with Zen 5 CPU in an AM4 package

10 core Lion Cove CPU with AVX-512 and quad channel RAM

295K that can run at least one core at 6 GHz but it cannot sustain that speed for more than a few seconds

Zen 5 CPU with enhanced IOD that runs EXPO CUDIMM DDR5-10500

8C/16T Ice Lake mobile chip with eDRAM

Did I miss something?

You've gone bonkers. The AM4/5 stuff probably existed for testing purposes. A Tejas 7GHz CPU booting Windows 11 without TPM or POPCNT? Come on.

coercitiv · May 29, 2025

Thunder 57 said:
Windows 11 without TPM or POPCNT? Come on.

AFAIK TPM can still be bypassed, POPCNT cannot.

igor_kavinski · May 29, 2025

Thunder 57 said:
A Tejas 7GHz CPU booting Windows 11 without TPM or POPCNT? Come on.

23H2 doesn't need POPCNT compatible CPU and TPM isn't a hard requirement.

igor_kavinski · May 29, 2025

I bet @NostaSeronx has some cool info about hardware that never saw the light of day but exists to this day and still booting.

Thunder 57 · May 29, 2025

igor_kavinski said:
I bet @NostaSeronx has some cool info about hardware that never saw the light of day but exists to this day and still booting.

Oh right like Tunnelborer.

NostaSeronx · May 30, 2025

igor_kavinski said:
I bet @NostaSeronx has some cool info about hardware that never saw the light of day but exists to this day and still booting.

I am not that much of a hobbyist.

Thunder 57 said:
Oh right like Tunnelborer.

Brisbane = Ballpeenhammer cores
Sparta = Drillhammer core

Construction machines is just even more weird in naming.

65nm -> 45nm test products also had construction core names.

20nm/14nm Bulldozers were only officially dropped in 2015. The 2012 switch to Zen only cut the Server products. The re-iteration is likely to be pushed into the variations of Zen. As clustered is the only way to go.

Thunder 57 · May 30, 2025

NostaSeronx said:
I am not that much of a hobbyist.

Brisbane = Ballpeenhammer cores
Sparta = Drillhammer core

Construction machines is just even more weird in naming.

65nm -> 45nm test products also had construction core names.

20nm/14nm Bulldozers were only officially dropped in 2015. The 2012 switch to Zen only cut the Server products.

More fake news. Provide a source and I will admit I am wrong.

soresu · May 30, 2025

NostaSeronx said:
As clustered is the only way to go

Given we 3 major µArch designs into Zen (1 -> 3 -> 5) with at least 6 and 7 and likely 8 on the horizon I think that the likelihood of CMT ever coming back to an AMD CPU is pretty much non existent at this point.

If anything SMT seems to be showing off even more with Zen5, so I don't see why they would deviate from the path they are on.

DZero · May 30, 2025

NTMBK said:
You forgot Kaveri with a quad-channel memory controller and a big boi GPU. I refuse to believe that AMD didn't consider this back when they were designing the APUs for the PS4 and XBox One.

I heard that FX was going to continue with Kaveri and Carrizo being quad module?

NostaSeronx · May 30, 2025

soresu said:
Given we 3 major µArch designs into Zen (1 -> 3 -> 5) with at least 6 and 7 and likely 8 on the horizon I think that the likelihood of CMT ever coming back to an AMD CPU is pretty much non existent at this point.

If anything SMT seems to be showing off even more with Zen5, so I don't see why they would deviate from the path they are on.

Chip-level Multithreading is not the original goal for Bulldozer. It was Cluster-based Multithreading, which was the target. Before, it was changed in later 2007, fully roadmap'd by 2008.

Zen5:
2x Op cache pipes
2x instruction fetch/decode pipes

Zen3:
2x FPU datapath (2x FPSCH/MUL/ADD/MISC)

Zen5:
3x FPU datapath (Std have own cluster)

Clustered architecture. However, it will be extremely awkward for this not to have 2-threads given; 2x LD, 2x LD/ST, 2x ST.

"Looking at all these "K-8" patents issued we must conclude that considerable work has gone into this architecture. The real Hammers to be released at the end of next year may include maybe only a subset of all these features. This doesn't mean that the designers of Hammer's successor K9 (code-named GreyHound?) won't continue on the base of this work. The double core concept as shown in the patents is not new. The Alpha EV6 also has a double integer core for much the same reasons as given in the "K-8" patents. The contents of both register files is kept identical so that both cores can work on the same (single thread) program. Such a double core by itself doesn't say anything about SMT." -- 2001

US6256721B1 - Register renaming in which moves are accomplished by swapping tags - Google Patents

An apparatus for accelerating move operations includes a lookahead unit which detects move instructions prior to the execution of the move instructions (e.g. upon selection of the move operations for dispatch within a processor). Upon detecting a move instruction, the lookahead unit signals a...

patents.google.com

US6266763B1 - Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values - Google Patents

A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e.g. floating point, multimedia...

patents.google.com

In one embodiment, execution core 40A and execution core 40B are symmetrical. Each execution core 40 may include, for example, a floating point add unit, a floating point multiply unit, two integer units, a branch unit, a load address generation unit, a store address generation unit, and a store data unit.

FP-ADD -> FP-MUL -> two integer units -> one branch. Where by the time BD(2005-2007) was done both FPU/AGUs were given their own clusters.

Where the single FPU cluster in the above core is the Vec cluster.

DZero said:
I heard that FX was going to continue with Kaveri and Carrizo being quad module?

Kaveri's GDDR5 was tri-module. While Komodo onwards was penta-module, ala Terramar(32nm)/Dublin(28nm) on Porto/Sepang(32nm)/Macau(28nm) on Luxembourg. With the final release of information being a octo-module.

This would actually be 40h-4Fh. As it is the sequel to 20h-2Fh 5-module. Excavator employees stated this one would be Steamroller(28nm) and Excavator(20nm). Where the Excavator one would have its own models compared to Steamroller 40h-4Fh.

soresu · May 30, 2025

NostaSeronx said:
It was Cluster-based Multithreading

That's what I'm talking about when I say CMT.

NostaSeronx · May 30, 2025

soresu said:
That's what I'm talking about when I say CMT.

You are referring mainly only to Bulldozer. Which in its only in market state was only ever Chip-level Multithreading.

Zen3 = Two Floating-point Clusters can be used on a single-thread or on seperate threads. +50% throughput on FP versus prior-FPU(Zen2/Zen3 = same AVX256 layout) design.
Zen2 = Monolithic FPU
Zen3 = Clustered FPU

Where Zen5 comes in and adds a Steamroller-esque front-end to the Zen cores. Which in its current state is closer to Chip-level Multithreading. Where it is actually meant to operate as a Cluster-based Multithreading solution. Two-threads when needed, but primarily used to increase single-thread perf/eff.

The general path of Zen is more aggressively Cluster-based Multithreading. Than the market Bulldozer ever was.

Zen = K8
Zen2 = Greyhound
Zen3 = Bulldozer (ideal form, clustered FPU since that is big workload. Rather than integer workloads.)
Zen5 = Steamroller (not ideal form, but has been stated that both front-end pipelines will be single-threaded usable.)
[If nothing happens, Zen7 based on the above is the ideal Tunnelborer]

~~~~
"Clustered microarchitectures are an effective way to deal with wire delays and complexity. Some conventional processors such as the Alpha 21264 have implemented a clustered integer execution core. Clustered microarchitectures have been the focus of numerous recent proposals for increasing performance or reduce power dissipation.

Many authors have proposed to use the increasing transistor budget on a chip to exploit TLP, in addition to ILP (instruction-level parallelism). However, not much work has been published based on the idea of combining both paradigms in a synergistic way: clustering and multithreading." -- Intel Labs in 2004, pre-research for Pentium 5 project (Tejas (P4) <-> Nehalem (P5, not Core i variant))

"While it is not clear that an 8-issue general-purpose single-threaded processor would be viable due to the lack of inherent ILP in most applications, an SMT processor can easily take full advantage of an 8-issue, 16-issue, or wider processor – if we can build them with-out sacrificing clock speed.

A clustered multithreaded architecture, then, has the ability to exploit both thread-level parallelism and instruction-level parallelism, yet still maintain high clock rates to maximize overall throughput." - Also 2004, some random school maybe.

Cluster-based Multithreading is Simultaneous Multithreading, but with clusters.

igor_kavinski · May 30, 2025

NostaSeronx said:
Cluster-based Multithreading is Simultaneous Multithreading, but with clusters.

So an SMT+CMT CPU will juggle two threads using its SMT logic and juggle multiple instructions in each thread using the CMT logic, correct? And the bane of both is branchy code?

Thibsie · May 30, 2025

igor_kavinski said:
I bet @NostaSeronx has some cool info about hardware that never saw the light of day but exists to this day and still booting.

You woke him. Happy ?

igor_kavinski · May 31, 2025

Thibsie said:
You woke him. Happy ?

Too much sleep can be a health hazard!

NostaSeronx · May 31, 2025

igor_kavinski said:
So an SMT+CMT CPU will juggle two threads using its SMT logic and juggle multiple instructions in each thread using the CMT logic, correct? And the bane of both is branchy code?

Branchy apps in Cluster-based Multithreading will have a lower hit on performance than Simultaneous Multithreading.

SMT = single pipeline, single queues ==> division of light threads compete for same resources.
CMT = multiple pipelines, multiple queues ==> division of light threads are on different resource islands.

Simultaneous Multithreading improvement of throughput with second thread = 1.3x
Multi-core improvement of throughput with second thread = 1.7x
Cluster-based Multithreading improvement of throughput with second thread = 1.8x

The only known issue for CMT is its baseline component, clustered microarchitecture. This clustered design has penalties on heavy (high-ILP/low-branch) workloads. As the singlethread is crossing both clusters, and thus is hit by cross-cluster penalty. Zen3's design proved this is not worthwhile fear. FPU Execution Cluster 0: SCH0-PRF0-P0/P2/P4 and FPU Execution Cluster 1: SCH1-PRF1-P1/P3/P5 setup had more beneficial end results.

The decision for clustered microarchitectures was to retain speed at similar power.
On same node, monolithic;
2-ALU = baseline
4-ALU = 2x lower frequency
6-ALU = 4x lower frequency
Where a single complete node shrink can recover most of the first upgrade. While two complete node shrinks are needed for the second upgrade.

2-ALU vs 2-ALU = baseline, N0
2x2ALU vs 4-ALU = 15% faster or half-power, N1
3x2ALU vs 6-ALU = 15% faster or half-power, N2
Most people were focused on the speed-demon aspect, and not that it reduced power at same performance significantly.

DZero · Jun 4, 2025

@NostaSeronx , question, there were rumours that there was supposed to be a Steamroller based FX chip or an tri module / hexa core Carrizo chip?

NostaSeronx · Jun 4, 2025

DZero said:
@NostaSeronx , question, there were rumours that there was supposed to be a Steamroller based FX chip or an tri module / hexa core Carrizo chip?

Yes, referenced in text over here: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...dont-see-why-it-wouldnt.2630153/post-41455155

GDDR5 A0=DCT0
GDDR5 A1=DCT2
GDDR5 B0=DCT3
GDDR5 B1=DCT1

Where it is actually GDDR5 Mainstream (GDDR5M);
GDDR5M = 51.2 mm2 for 5 GT/s
DDR4 = 76 mm2 for 2.66 GT/s

AMD Kaveri Docs Reference Quad-Channel Memory Interface, GDDR5 Option

www.anandtech.com

DCT0+DCT2 = 64-bit in total
DCT1+DCT3 = 64-bit in total
Maximum width of GDDR5M = 32-bit for every channel. While it shared the memory pods x8/x16 with DDR3/DDR4.

DIMM = x16+x16, clamshell x16+x16 for 2 gigabytes and 4/3.6 gigatransfers at maximum cost-effectiveness.

GDDR5M slots are upright, not laid flat like mobile memory.

Top, not bottom.

DZero · Jun 4, 2025

NostaSeronx said:
Kaveri's GDDR5 was tri-module. While Komodo onwards was penta-module, ala Terramar(32nm)/Dublin(28nm) on Porto/Sepang(32nm)/Macau(28nm) on Luxembourg. With the final release of information being a octo-module.
View attachment 124573
This would actually be 40h-4Fh. As it is the sequel to 20h-2Fh 5-module. Excavator employees stated this one would be Steamroller(28nm) and Excavator(20nm). Where the Excavator one would have its own models compared to Steamroller 40h-4Fh.

Welp, that explains the potential of it... it had room for a Tri Module processor for desktop and even laptops. Maybe releasing with Carrizo or Bristol, could have given a better good bye than the current situation.

I mean, of course AMD was behind Intel, but giving a Tri Module/Hexa Core processor could catter more sellings in the notebook department going with the 45W option and the desktop department, even without strong overclock, it could sell better than expecting.

aigomorla · Wednesday at 5:23 PM

im actually waiting for Ram to go obselete with Gen7 or Gen8 nVME's replacing RAM / Storage all together.
Gen5 is i think considered faster then DDR4 in a RAID-0 utilizing a full 16x PCI-E slot.

I think by Gen7 we may see the DDR slot disappear all together.

Discussion [Speculation] Working silicon that must exist because I don't see why it wouldn't

Lifer

Golden Member

Lifer

Lifer

Diamond Member

Diamond Member

Diamond Member

Lifer

Lifer

Diamond Member

Diamond Member

Diamond Member

Diamond Member

Golden Member

Diamond Member

Diamond Member

Diamond Member

Lifer

Golden Member

Lifer

Diamond Member

Golden Member

Diamond Member

Golden Member

CPU, Cases&Cooling Mod PC Gaming Mod Elite Member