Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Doug S · Thursday at 1:08 AM

Thunder 57 said:
OK, but they doubled it with Prescott and it clocked faster. Or did they get away with that because of the longer pipeline? Or something else?

Prescott was on a new process, back when "a new process" really meant something.

Cheesecake16 · Thursday at 1:13 AM

igor_kavinski said:
Since @Cheesecake16 is here, Imma gonna ask the question that's on everybody's mind: How mad are you that Intel messed up so badly? Do you believe Nova Lake will fix everything that's been wrong with Intel CPU architectures since Skylake?

Why would I be mad?

Chips are hard... I get that... Look at the Raptor Lake issues, that ended up being an issue with the clock tree which is incredibly complex and I could see any company running into that issue...

I think that Intel made decisions with Arrow Lake that didn't quite pan out as well as they were hoping for the market that Arrow Lake is designed to target with regards to the performance of the architecture... tho with regards to the IO/PCIe capabilities, I think it's very competitive and better then what AMD has at the moment. Yet those same design choices have served Lunar Lake quite well in its target market, so it's tradeoffs like all engineering is...

Do I think Nova Lake will "fix everything that's been wrong with Intel CPU architectures since Skylake"? I don't know... I think that Intel will improve their D2D interconnect and will make their cores more attuned to what a chiplet architecture has to deal with, mainly bigger buffers to handle the increased latency of a chiplet fabric, along with improving the bandwidth that each P-Core can injest which was an odd weakness for the Lion Cove cores... But do I think that will "fix all of the issues?" I don't know...

511 · Thursday at 6:44 AM

@Cheesecake16
What do you think about this than it is a leak from Intel forums basically lowering the Ring stops for cores from 12 to 8. This will help with the L3 Ring latency as well and would dramatically improve the PPA for Core+L2?

https://twitter.com/x/status/1930311847023919424

coercitiv · Thursday at 7:04 AM

511 said:
@Cheesecake16
What do you think about this than it is a leak from Intel forums basically lowering the Ring stops for cores from 12 to 8. This will help with the L3 Ring latency as well and would dramatically improve the PPA for Core+L2?

I struggle to find a leak in what you posted. As far as the idea to share stops for P cores, it sounds like cutting your toes to perfectly fit the bed: the ring may be fine, but the suffering will move elsewhere.

I'm open to opinions on why a shared L2 could be worth exploring, but I fail to see how moving a bottleneck from the ring to core clusters would help performance in latency sensitive workloads. (games, we always mean games)

511 · Thursday at 7:32 AM

coercitiv said:
I struggle to find a leak in what you posted. As far as the idea to share stops for P cores, it sounds like cutting your toes to perfectly fit the bed: the ring may be fine, but the suffering will move elsewhere.

I'm open to opinions on why a shared L2 could be worth exploring, but I fail to see how moving a bottleneck from the ring to core clusters would help performance in latency sensitive workloads. (games, we always mean games)

It's not a leak per say but the guy's being a Chad so I thought he would definitely be right 😂.

LightningZ71 · Thursday at 8:02 AM

coercitiv said:
I struggle to find a leak in what you posted. As far as the idea to share stops for P cores, it sounds like cutting your toes to perfectly fit the bed: the ring may be fine, but the suffering will move elsewhere.

I'm open to opinions on why a shared L2 could be worth exploring, but I fail to see how moving a bottleneck from the ring to core clusters would help performance in latency sensitive workloads. (games, we always mean games)

Something to consider is that the P cores have kind of been adding an additional level of cache internally lately, roughly a level "0" cache in addition to the L1. Assuming that they can keep L2 cache latency low, and bandwidth high for each core, as long as they aren't hitting the L2 more than 40-50% of the time per core attached to it, it shouldn't be too bad. There are a couple of people out there that have done some limited gaming runs on just the e-cores with a modest overclock and they haven't looked too bad, even if those clusters aren't optimized for that sort of activity.

Geddagod · Thursday at 9:25 AM

511 said:
@Cheesecake16
What do you think about this than it is a leak from Intel forums basically lowering the Ring stops for cores from 12 to 8. This will help with the L3 Ring latency as well and would dramatically improve the PPA for Core+L2?

https://twitter.com/x/status/1930311847023919424
View attachment 124905

Is that dude not just a random user? The rest of the thread seems to be Intel just saying we can't comment on future products.
I also don't think the leak specifies that it would lower the ring stops either, I think that's just speculation from the rumor.

igor_kavinski · Thursday at 9:28 AM

Sharing cache between the Lion Cove cores could work if a single core isn't taking advantage of it much on its own. Maybe increase it to 4MB per two cores and it could potentially reduce ring traffic in multicore workloads that rely on a lot of cache hits.

511 · Thursday at 9:52 AM

igor_kavinski said:
Sharing cache between the Lion Cove cores could work if a single core isn't taking advantage of it much on its own. Maybe increase it to 4MB per two cores and it could potentially reduce ring traffic in multicore workloads that rely on a lot of cache hits.

Not to forget by sharing caches you cut the number of P cores on a Ring by half lol

LightningZ71 · Thursday at 10:30 AM

A couple of things:
Increasing the L2 to 4MB might require an increase in access latency for it. That's going to get magnified when shared between two or more cores.
Binning might be an issue. What do you do if you've got a core or two that don't meet spec? Do you kill two next to each other, or does your topology allow for a pair to be asymetric with the rest of the stops? To date, we haven't seen intel push a chip bin out the door for the e core clusters that wasn't all or nothing. I expect that the true impact might be minimal as they haven't offered a processor with an odd number of P cores yet (save for the Pentium and Celerons that had only a single P core active). They'd probably just fuse them off in pairs. With good yields, it shouldn't have a notable impact.

511 · Thursday at 11:00 AM

LightningZ71 said:
A couple of things:
Increasing the L2 to 4MB might require an increase in access latency for it. That's going to get magnified when shared between two or more cores.
Binning might be an issue. What do you do if you've got a core or two that don't meet spec? Do you kill two next to each other, or does your topology allow for a pair to be asymetric with the rest of the stops? To date, we haven't seen intel push a chip bin out the door for the e core clusters that wasn't all or nothing. I expect that the true impact might be minimal as they haven't offered a processor with an odd number of P cores yet (save for the Pentium and Celerons that had only a single P core active). They'd probably just fuse them off in pairs. With good yields, it shouldn't have a notable impact.

I think it will be fairly straightforward they do it with 265K they disable 2E cores so I think it is possible to disable 1 as well.

LightningZ71 · Thursday at 11:53 AM

511 said:
I think it will be fairly straightforward they do it with 265K they disable 2E cores so I think it is possible to disable 1 as well.

265K has three clusters of 4 each enabled.

511 · Thursday at 12:44 PM

LightningZ71 said:
265K has three clusters of 4 each enabled.

Oh yeah my bad I mistook that so looks like both the cores will be disabled

DavidC1 · Thursday at 11:37 PM

Thunder 57 said:
OK, but they doubled it with Prescott and it clocked faster. Or did they get away with that because of the longer pipeline? Or something else?

Prescott may have doubled the L1D capacity, but it had 4 cycle latency. Northwood's L1D was 2 cycles. For all the additions they got maybe 10% clock gain and basically sidegrade performance.

If Intel just stuck to 20 pipeline stages with all the enhancements, it would have ended up being a more efficient and faster chip. Of course they were under the delusion they could easily reach 6-7GHz when simple glance at OC records would show those frequencies are only reached when silicon is at low enough temperatures. Don't need fancy engineering degree to know that.

coercitiv said:
I struggle to find a leak in what you posted. As far as the idea to share stops for P cores, it sounds like cutting your toes to perfectly fit the bed: the ring may be fine, but the suffering will move elsewhere.

It also doesn't guarantee dramatic reduction in L3 latency. 4 hop reduction is just 4 cycle reduction, which is nothing when you consider it's in the 80 cycles range for Arrowlake.

DavidC1 · Thursday at 11:38 PM

Intel draws a line in the sand to boost gross margins — new products must deliver 50% gross profit to get the green light

Lip-Bu Tan is "laser-focused" on getting Intel back to maximizing shareholder value

www.tomshardware.com

Michelle Johnston Holthaus, CEO of Intel Products, announced at Bank of America's global technology conference that Intel is no longer approving new projects that cannot be proven to earn at least 50% gross margin "based on a set of industry expectations."

Yes, because focusing on gross margins in the Barrett/Otellini/Kraznich days ended up being so awesome for them. They were near 65% at one point.

You can't just focus on margins and profits as an engineering company. Most research and development will not end up as a real product, and many product lines will only benefit indirectly.

You don't get to succeed and have high margins just because you "aim" and hope for it. It's a reward for a good product and your hard work.

I'm not just criticizing this company for the heck of it. I'm doing it because they deserve it. They were leaders in the area of computing. They were the first to nearly every new standard in the market. They truly drove the industry forward. Now they are an increasingly dim light.

Thunder 57 · Friday at 12:48 AM

DavidC1 said:
Intel draws a line in the sand to boost gross margins — new products must deliver 50% gross profit to get the green light

Lip-Bu Tan is "laser-focused" on getting Intel back to maximizing shareholder value

www.tomshardware.com

Yes, because focusing on gross margins in the Barrett/Otellini/Kraznich days ended up being so awesome for them. They were near 65% at one point.

You can't just focus on margins and profits as an engineering company. Most research and development will not end up as a real product, and many product lines will only benefit indirectly.

You don't get to succeed and have high margins just because you "aim" and hope for it. It's a reward for a good product and your hard work.

I'm not just criticizing this company for the heck of it. I'm doing it because they deserve it. They were leaders in the area of computing. They were the first to nearly every new standard in the market. They truly drove the industry forward. Now they are an increasingly dim light.

I wonder where that leaves ARC. I mean they need something for their iGPU's. But will they bother with dGPU's anymore? Doesn't seem likely with this mandate. A shame too as a third player was always going to be welcomed.

Joe NYC · Friday at 2:37 AM

DavidC1 said:
Intel draws a line in the sand to boost gross margins — new products must deliver 50% gross profit to get the green light

Lip-Bu Tan is "laser-focused" on getting Intel back to maximizing shareholder value

www.tomshardware.com

Yes, because focusing on gross margins in the Barrett/Otellini/Kraznich days ended up being so awesome for them. They were near 65% at one point.

You can't just focus on margins and profits as an engineering company. Most research and development will not end up as a real product, and many product lines will only benefit indirectly.

You don't get to succeed and have high margins just because you "aim" and hope for it. It's a reward for a good product and your hard work.

I'm not just criticizing this company for the heck of it. I'm doing it because they deserve it. They were leaders in the area of computing. They were the first to nearly every new standard in the market. They truly drove the industry forward. Now they are an increasingly dim light.

I wonder how serious Intel is about the focus on > 50% instead of market share, which would imply exit or downsizing in number of divisions.

Client dGPU as good as gone, but as it happens, the entire sever CPU division of Intel is way under that 50% bar.

The margin dollars of lower (than 50%) Gross Margin products still add up to support Intel's cost structure.

If Intel were to exit or raise prices to get to that 50% margin, it would be followed by market share losses and revenue loses and would likely lead to necessity for another round of layoffs.

It is hard to see a way for Intel to break this cycle.

DrMrLordX · Friday at 3:34 AM

Joe NYC said:
I wonder how serious Intel is about the focus on > 50% instead of market share, which would imply exit or downsizing in number of divisions.

Client dGPU as good as gone, but as it happens, the entire sever CPU division of Intel is way under that 50% bar.

Exactly. Intel's margins have taken a beating thanks to the problems they've had up through Sapphire Rapids. Have margins even improved for Emerald or Granite Rapids?

coercitiv · Friday at 4:47 AM

Joe NYC said:
I wonder how serious Intel is about the focus on > 50% instead of market share, which would imply exit or downsizing in number of divisions.

Client dGPU as good as gone, but as it happens, the entire sever CPU division of Intel is way under that 50% bar.

I hope it has more to do with the design decisions they make to ensure a product is financially viable in a competitive environment: tile breakdown, transistor budget, packaging technology, memory etc. LNL might have had trouble using mem on package while passing this check, for example. I also doubt MTL would have seen the light of day. Or Sapphire Rapids, lol. In this scenario the dGPUs are still viable, but the teams need to be focused on efficient designs.

One of the big issues Intel had in the past was trying to catch the competition by leapfrogging them. I've talked about this before, Intel never copied or planned for gradual progress that would improve their chances to reach top spot, they came up with their own killer approach that was supposed to leave the competition behind. This usually involved complicated and expensive designs. Ambition led to delays, and delays led to bad products. Meanwhile the competition made smaller and somewhat predictable steps, but with good speed and pacing.

Remember the Intel KPI that Lip-Bu Tan found out after becoming CEO - the size of your team. Intel's people measured success by headcounts, and your team size grows if your product is a complex over-promising mess. Re-focusing on financial viability of products might be his way of trying to course-correct the toxic corporate culture (assuming this is part of a broader strategy, and also assuming the 50% figure was floated just to impress the audience, otherwise I'd be tempted to agree with @DavidC1 )

DavidC1 · Friday at 5:24 AM

coercitiv said:
Remember the Intel KPI that Lip-Bu Tan found out after becoming CEO - the size of your team.

How do they keep missing these massive, obvious flaws over, and over, and over again? How did they not find it out during Gelsinger's time? How did Otellini not know this?

The inefficiency regarding their IDM operation was a revelation too. HOW? Just how? What else are they not telling us? Bringing "grovian" accountability as said by Gelsinger is another matter. Why did not do it before?

Are they so messy, and filled with bureaucratic layers that it takes the CEO's multiple years to figure few of them out? Whatever magic bullet is sent to supposedly save Intel just gets shot out of the sky before it even has a chance to grow to maturity.

At what point do they need completely overhaul the company, like turn 80%+ of it over and do it nearly from scratch?

coercitiv said:
Ambition led to delays, and delays led to bad products. Meanwhile the competition made smaller and somewhat predictable steps, but with good speed and pacing.

So part of the reason they needed to do this is because they eventually get themselves into such a position. We didn't need a massive Netburst-->Core 2 jump. It could have been more gradual. Same with Atom and mobile. Same with process technology.

What's the fundamental reason? Some flaws in thinking, someone, or some group is the issue. Whatever it is, it leads them to make radical leaps because they've been stagnating for whatever reason. Lazyness, squeezing every penny, mismanagement, it doesn't matter.

511 · Friday at 6:40 AM

Thunder 57 said:
I wonder where that leaves ARC. I mean they need something for their iGPU's. But will they bother with dGPU's anymore? Doesn't seem likely with this mandate. A shame too as a third player was always going to be welcomed.

Arc dGPU wouldn't be killed if you ask me where are they going to drive the SW Stack for their supposed rack scale solution it's gotta come from dGPU Client or Server afaik they only got client GPUs for that.

DrMrLordX said:
Exactly. Intel's margins have taken a beating thanks to the problems they've had up through Sapphire Rapids. Have margins even improved for Emerald or Granite Rapids?

The issue for Sapphire Rapid/Emerald margin are the delays GNR Shoud be an improvement cause it's at least competitive and has very few clear advantage unlike SPR which didn't have any but big dies are slower to ramp and in general the ramp has been slow for their I3/I4 nodes they are only 5% for the EUV mix last quarter earnings calls.

coercitiv said:
I hope it has more to do with the design decisions they make to ensure a product is financially viable in a competitive environment: tile breakdown, transistor budget, packaging technology, memory etc. LNL might have had trouble using mem on package while passing this check, for example. I also doubt MTL would have seen the light of day. Or Sapphire Rapids, lol. In this scenario the dGPUs are still viable, but the teams need to be focused on efficient designs.

One of the big issues Intel had in the past was trying to catch the competition by leapfrogging them. I've talked about this before, Intel never copied or planned for gradual progress that would improve their chances to reach top spot, they came up with their own killer approach that was supposed to leave the competition behind. This usually involved complicated and expensive designs. Ambition led to delays, and delays led to bad products. Meanwhile the competition made smaller and somewhat predictable steps, but with good speed and pacing.

The Intel way 😂🤣

coercitiv said:
Remember the Intel KPI that Lip-Bu Tan found out after becoming CEO - the size of your team. Intel's people measured success by headcounts, and your team size grows if your product is a complex over-promising mess. Re-focusing on financial viability of products might be his way of trying to course-correct the toxic corporate culture (assuming this is part of a broader strategy, and also assuming the 50% figure was floated just to impress the audience, otherwise I'd be tempted to agree with @DavidC1 )

I hope that as well and I think Royal Core was one such thing it was a financial mess I am surprised it wasn't killed sooner.

DavidC1 said:
How do they keep missing these massive, obvious flaws over, and over, and over again? How did they not find it out during Gelsinger's time? How did Otellini not know this?

The inefficiency regarding their IDM operation was a revelation too. HOW? Just how? What else are they not telling us? Bringing "grovian" accountability as said by Gelsinger is another matter. Why did not do it before?

Are they so messy, and filled with bureaucratic layers that it takes the CEO's multiple years to figure few of them out? Whatever magic bullet is sent to supposedly save Intel just gets shot out of the sky before it even has a chance to grow to maturity.

Yeah even I am baffled by the foundry revelation they didn't do proper validation design spoonfed by foundry, foundry was supposed to fix Design mess, foundry cultural rot this is horrendous that it took until pat to get this sorted.

igor_kavinski · Friday at 8:31 AM

coercitiv said:
Remember the Intel KPI that Lip-Bu Tan found out after becoming CEO - the size of your team. Intel's people measured success by headcounts, and your team size grows if your product is a complex over-promising mess. Re-focusing on financial viability of products might be his way of trying to course-correct the toxic corporate culture (assuming this is part of a broader strategy, and also assuming the 50% figure was floated just to impress the audience, otherwise I'd be tempted to agree with @DavidC1 )

Very thoughtful post! And this is precisely what Keller described about managing teams. The bigger they are, the harder it becomes to manage them. Communication between the team members breaks down. And I don't know if he said this but I've seen myself that people will band together in their own groups inside that huge team and they won't play nice with the other groups and this is how dirty politics start bringing down the whole skyscraper.

igor_kavinski · Friday at 8:37 AM

DavidC1 said:
What's the fundamental reason? Some flaws in thinking, someone, or some group is the issue. Whatever it is, it leads them to make radical leaps because they've been stagnating for whatever reason. Lazyness, squeezing every penny, mismanagement, it doesn't matter.

These leaps were possible before because they were basically betting on multiple teams doing the same thing in the hopes that at least one of them will hit the jackpot. This is how Core happened and same reason why Skymont came out so strong. But with LBT's new focus on feasible margins, they could potentially end up betting on the wrong horse and cancel the wrong team(s). It's going to be a very ugly bloodbath unless LBT is a maestro at this sort of strategic planning and culling.

511 · Friday at 9:17 AM

igor_kavinski said:
These leaps were possible before because they were basically betting on multiple teams doing the same thing in the hopes that at least one of them will hit the jackpot. This is how Core happened and same reason why Skymont came out so strong. But with LBT's new focus on feasible margins, they could potentially end up betting on the wrong horse and cancel the wrong team(s). It's going to be a very ugly bloodbath unless LBT is a maestro at this sort of strategic planning and culling.

No no hold you your horses there are only two teams for CPU IP also LBT is not like that.

igor_kavinski · Friday at 9:30 AM

511 said:
No no hold you your horses there are only two teams for CPU IP

You don't know that for sure. They don't have to reveal that information publicly, especially about R&D stuff that could give them an edge.

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