LPDDR has greater benefit to APUs, so especially with the new Halo segment I wouldn't be surprised to see AMD pushing that envelope a bit faster.I doubt DDR6/LPDDR6 by both AMD/Intel before 2028
My problem is availability and the priceLPDDR has greater benefit to APUs, so especially with the new Halo segment I wouldn't be surprised to see AMD pushing that envelope a bit faster.
True, that's always going to be an issue with the early adopter angle.My problem is availability and the price
My problem is availability and the price
I doubt DDR6/LPDDR6 by both AMD/Intel before 2028
My problem is availability and the price
Yes cause I don't see any next gen product before 2028 for both Intel/AMD maybe Razor Lake is 2027 but idk for sure.Seriously?
WE will seeBoth should be solved by the phone guys (specifically LPDDR6) way before that. Like in 2026. 2027 should not be a problem for Medusa Halo from price and availability POV.
I agree. I don't think that we will be seeing new memory support on Zen 6. I think that it will only happen with Zen 7 or beyond as it will likely require a socket change and most certainly new mbs.Yes cause I don't see any next gen product before 2028 for both Intel/AMD maybe Razor Lake is 2027 but idk for sure.
WE will see
If Zen 6 comes with a new IOD I would be very surprised if AMD actually ditches it within a single generation.I agree. I don't think that we will be seeing new memory support on Zen 6. I think that it will only happen with Zen 7 or beyond as it will likely require a socket change and most certainly new mbs.
I think theres a 99% chance Zen 6 gets a new IOD. What it brings, however, remains to be seen. Real CUDIMM support and possibly LP cores?If Zen 6 comes with a new IOD I would be very surprised if AMD actually ditches it within a single generation.
There are non-zero odds that there isn't a new IOD with Zen 6. And that would make sense if the timelines for DDR6 production line up for Z7.
They don't have to ditch it. Remember AM4? AM5 will continue to be supported and remain relevant for several years after the new socket launch for DDR6. Give at least two years for DDR6 widespread adoption and prices to normalize. Another two or even four years of post-DDR6 AM5 support. So the new IOD could be useful for something like 5 or 6 years.If Zen 6 comes with a new IOD I would be very surprised if AMD actually ditches it within a single generation.
I doubt DDR6/LPDDR6 by both AMD/Intel before 2028
Combination of 256-bit LPDDR5x and 384-bit LPDDR6 seems odd at first with extra 128-pin just reserved for LPDDR6 if LPDDR5x is being used.
A bug hybrid controller will take a lot of space it will be either DDR5 or DDR6 no in betweenIf you make a hybrid controller able to handle either LPDDR5X or LPDDR6 it delivers 24 bits of LPDDR6 or 16 bits of LPDDR5X, that's where that difference comes from.
Strix Halo already introduced its very own new "socket" (rather: new BGA pinout). Why shouldn't Medusa Halo come with yet another new BGA pinout also? A downside of course would be extra design and validation steps TBD by AMD and ODMs. The iGPU however would profit from the additional memory bandwidth. For work and recreation alike.
Since when AMD has MoP? Which products? Some FPGAs?Because of the short sighted decision on part of AMD to include Memory On Package. That one is biting AMD in the backside very badly..
Yes cause I don't see any next gen product before 2028 for both Intel/AMD maybe Razor Lake is 2027 but idk for sure.
Since when AMD has MoP? Which products? Some FPGAs?
Zen 6 is raising core counts up by 50%. DDR5 8000 raises memory bandwidth by 43%. Seems like that covers the additional bandwidth considering that Zen 5 is RARELY bandwidth constrained and is MUCH more performance dependent on memory LATENCY.If Zen 6 comes with a new IOD I would be very surprised if AMD actually ditches it within a single generation.
There are non-zero odds that there isn't a new IOD with Zen 6. And that would make sense if the timelines for DDR6 production line up for Z7.
Funny that Intel totally threw away their RAM latency advantage. No one there had the courage to put a stop to the madness of tile architecture when it wasn't ready for prime time.Lowering the main memory latency (as the designers of ARL can attest to) is a really big deal.
Memory latency and bandwidth are dependent variables of one another. The reason people don't see large bandwidth increases is because the fabric width and clock speed limits bandwidth per CCD. If most systems are running at an FCLK of 2000-2200 MHz you're being duped if you think that means higher memory bandwidth isn't impactful. A 32 byte interface at 2 GHz gives you 64 GB/s. 50% of the theoretical bandwidth that a 128 bit 8 Gbps memory bus supplies. You could only saturate that if you have a Dual CCD chip, and games will isolate themselves to one CCD where possible.Zen 6 is raising core counts up by 50%. DDR5 8000 raises memory bandwidth by 43%. Seems like that covers the additional bandwidth considering that Zen 5 is RARELY bandwidth constrained and is MUCH more performance dependent on memory LATENCY.
DDR5 Memory Performance Scaling with AMD Zen 5
Our AMD Zen 5 Memory Scaling Review examines six different DDR5 memory speeds, including DDR5-8000, DDR5-6400 1:1, DDR5-6400 CL28 and others. We looked into how these speeds impact performance in gaming at four resolutions and a wide range of application workloads.www.techpowerup.com